Issue link: https://resources.pcb.cadence.com/i/1541046
17. Using a Continuous Ground Plane How To Implement 1. Dedicate an internal layer as a solid ground plane: f In 4-layer boards, dedicate the second layer (L2) as GND; in 6-layer and higher, have at least one solid GND adjacent to all critical signal layers. f Avoid routing signal or power traces on the ground plane layer itself unless absolutely necessary. 2. Keep the ground plane as unbroken as possible: f Avoid large anti-pads, long slots, or large cutouts in the ground plane. If you must create a cutout (for high-voltage creepage or a slot antenna), carefully control where return currents will flow and provide alternative return paths. f Never split ground planes unless absolutely required by the system architecture; if a split is necessary, tie grounds together at a single, well-defined point (star point). 3. Stitch copper pours to the main ground: f On outer layers or where you use ground pours, connect them to the internal ground plane with frequent vias (every 5-10 mm; every 2-3 mm for high-speed/RF). f Ensure every ground pour or polygon is tied to the main ground net and does not "float" or become an isolated island. 4. Route high-speed signals adjacent to ground: f Plan the stackup so that all controlled-impedance signals have a solid ground reference directly beneath them. f When changing layers (e.g., via), add stitching ground vias nearby to provide a local return path, minimizing loop area. 5. Plan for split planes in mixed-signal or isolated systems: f If you must separate analog and digital grounds (per datasheet or system requirement), split only on the ground plane, never on the signal layer. Tie the splits together at a controlled point; usually under or near an ADC (Analog to Digital Converter), codec, or mixed-signal IC per vendor guidance. f Route signals so they never cross a split; this prevents return current from having to " jump the gap," which is a major EMI and noise risk. 6. Check and review for continuity: f Use your EDA tool's plane visualization or cross-section viewer to confirm there are no "dead zones," isolated islands, or unwanted splits in your ground. f After routing, re-run these checks before final signoff and before exporting for SI/EMC simulation. Common Pitfalls, Their Impact, and How to Avoid Them Common Pitfall How to Avoid it Accidental splits from poor via/pad placement Overlapping power and ground pads or using too many anti-pads can create ground "choke points" – Keep critical nets over continuous reference planes. Floating or fragmented ground pours Unconnected pours do not act as shields and can even resonate at RF – Ensure every pour ties to ground or connect with stitching vias. Routing high-speed signals over power or split planes Forces return currents into noisy or high-impedance paths, degrading SI/ EMI – Route over ground plane. Forgetting stitching vias Without them, ground references on different layers are isolated, especially in BGA fanouts or at board edges – Add regular ground stitching.