Issue link: https://resources.pcb.cadence.com/i/1541046
16. Reviewing and Optimizing Via Types, Sizes, and Counts How To Implement 1. Understand available via technologies: f Through-hole vias: Standard, lowest cost, used for most signals and power connections. Minimum drill size typically 0.2-0.3 mm (8-12 mil). f Blind vias: Connect the outer to inner layers, used in HDI/ fine-pitch, costlier and more complex. f Buried vias: Connect inner layers only, used for dense, multi-layer boards, and have an even higher cost. f Microvias: Laser-drilled, very small (0.1-0.15 mm), for HDI (High Density Interconnect), high speed, or fine-pitch BGA escape. f Via-in-pad: Used under fine-pitch BGAs, filled and capped, highest cost. 2. Set via sizes to meet electrical and manufacturing requirements: f Check fab's minimum and preferred finished hole size and annular ring. For high-speed or dense fanout, use the smallest reliable via. f For high-current paths (power, ground), use larger vias or multiple vias in parallel to keep resistance and temperature rise within limits. f For differential pairs, use matched via pairs to maintain impedance. 3. Optimize via count and placement: f Minimize vias on the critical net. Every via adds impedance discontinuity (typically 0.3-1.0 nH) and can degrade rise times. f On power and ground nets, use arrays of vias (stitching vias) to reduce voltage drop and EMI. f In BGA escapes, plan via placement early to avoid routing blockages or via "bunching." 4. Avoid via stubs and unconnected barrels: f For high-speed signals, reduce via stub length (unused via length below the signal's active layer) using backdrilling or blind/microvias. f Use filled and capped vias in via-in-pad structures to prevent solder wicking and shorts. 5. Check for manufacturability and cost trade-offs: f Every advanced via (blind, buried, microvia, via-in-pad) increases board cost and yield risk. Use only where needed. f Review via stackup and counts with your fabricator during stackup review to ensure all via types and sizes are buildable. 6. Simulate and validate: f For critical nets, include via models in the SI/PI simulation. f Use 3D viewers to check via height, clearance, and fit in mechanical constraints. Common Pitfalls, Their Impact, and How to Avoid Them Common Pitfall How to Avoid it Overusing advanced via types without need Raises cost and complexity – Use advanced via types only when density or performance demands it. Using too-small vias for power/high current Causes excessive IR drop and heat – Determine required current capacity and consider via stitching or larger vias. Creating via stubs in high-speed designs Degrades eye diagrams and increases reflections – Backdrill to remove unused barrel length or keep stubs short and route signals to inner layers closer to the surface. Ignoring via manufacturing constraints Can result in low yield or fabrication failures – Collaborate with your manufacturing partner early and often, and run DFM checks.