Issue link: https://resources.pcb.cadence.com/i/1541046
1.Establishing a Clean Design Rule Set How To Implement 1. Collect manufacturing data and standards: f Ask your PCB fabricator for their current capability tables ("capabilities matrix") that provides values for minimum trace width and spacing, finished via sizes, minimum annular ring, soldermask clearance, copper-to- board-edge, etc. f Identify applicable standards (IPC-2221 for general design, IPC-6012 for fabrication, IPC-7351 for land patterns, IPC-2222 for high-voltage, etc.). f If your product is safety-critical or high-voltage, gather creepage/clearance tables (from UL, IEC, IPC, or your fab). 2. Set basic physical rules: f Trace width/spacing: Typical minimums for mainstream fabs are 4-6 mil (0.10-0.15 mm), but always confirm with your fab and set a preferred value that gives you margin (e.g., design for six mil even if the fab can do four mil). f Via sizes: Standard minimum finished drill is 0.2-0.3 mm (8-12 mil); pad and annular ring should exceed the fab's minimum (often 6 mil or 0.15 mm ring). f Solder mask: Minimum dam (gap between mask and copper) is usually 3-4 mil (0.08-0.1 mm); set a preferred value slightly higher. f Copper-to-edge: Set a board edge clearance; most fabs require 10-20 mil (0.25-0.5 mm) between any copper and the cut edge to avoid shorts and exposed copper after routing. 3. Define net classes and custom constraints: f Group nets into classes by their needs: POWER (high current, wide traces), HIGH_SPEED (matched impedance, controlled lengths), ANALOG, SENSITIVE, I/O, etc. f Assign each class its own trace width, clearance, and (if needed) impedance. For example: HIGH_SPEED at 50 Ω single-ended, 100 Ω differential; POWER at 1 mm/40 mil width for 2 A current; ANALOG with increased clearance to digital. f Set via type (through, blind, buried, microvia) and count constraints per class 4. Special rules for critical items: f BGAs/Fine pitch: Define "room" constraints to reserve escape channels and enforce minimum via or component spacing. f High-voltage regions: Increase clearance and creepage; set explicit copper- to-copper and copper-to-edge rules. f Differential pairs: Define minimum/maximum pair spacing, length matching tolerance, and phase skew (e.g., keep intra-pair skew <5 mil for USB3, PCIe, DDR). 5. Enforce manufacturability: f Add rules for minimum silkscreen-to-copper (usually ≥ six mil), soldermask openings (for fine pitch), and paste reduction (for large thermal pads or fine-pitch). f Ensure via aspect ratio (drill/board thickness) is within fab limits (often ≤10:1). 6. Implement in your EDA tool: f Input all rules into the design constraints/rules manager. f Double-check that the online DRC is active and that errors are highlighted as you work. Test the rule system by drawing "bad" copper or placing features too close on purpose. 7. Document and communicate: f Export a summary of all rules and include it in your design package or project folder for reviews. f If working in a team, communicate any special rule exceptions or overrides. Common Pitfalls, Their Impact, and How to Avoid Them Common Pitfall How to Avoid it Using defaults Never trust tool defaults; they may not match your fab or the part's specs – Work with your fab early on to define your stackup and import their DFM/DRC rulesets. Setting rules too late Waiting until after placement/routing can result in dozens or hundreds of violations, some of which are hard to fix – Define and manage design rules (net classes, clearances, impedance widths, via types, etc.) before starting layout/ placement. Ignoring net class needs Assigning one "default" width to all nets fails to account for high current, high speed, or safety isolation – Classify these nets upfront. Assign width/spacing, return path constraints, and layer usage per class. Forgetting copper-to-edge Tight layouts can expose copper after routing, risking shorts and failed boards – Set board outline clearance rules or add a keepout around the perimeter.