Issue link: https://resources.pcb.cadence.com/i/1541046
14. Reviewing Silkscreen and Markings for Readability and Clarity How To Implement 1. Check designator placement and font size: f Place all component designators (U1, R23, C105, etc.) as close as possible to their respective part, but not under the part or on solderable pads. f Use a minimum font size per fab's recommendations - typically 40 mil (1 mm) height, 6 mil (0.15 mm) line width for readability after soldering. f For double-sided boards, distinguish top/bottom side markings by color or layer name. 2. Mark all polarity and orientation clearly: f For polarized parts (diodes, electrolytic/tantalum capacitors, LEDs), indicate the cathode/anode or positive terminal using both silkscreen and copper marks. f For ICs, especially multi-pin and non-symmetrical packages (QFN, BGA, connectors), add a clear pin 1 indicator - dot, bar, or chamfer mark. 3. Avoid printing on pads, vias, or keepouts: f Check for silkscreen over pads, exposed copper, test points, or mechanical holes; move or delete these items to prevent soldera- bility problems. f Run your EDA tool's DRC to flag silkscreen/pad overlaps. 4. Place special labels and regulatory marks: f Add logo, date code, revision level, RoHS/compliance, and serial number blocks as required. f If field-programming or calibration is needed, mark the relevant headers, jumpers, or areas clearly. 5. Label test points, jumpers, and fuses: f Assign and mark all test points (TP1, TP2…), configuration jumpers, and fuses for easy identification. 6. Check for crowding and conflicts: f On dense boards, check that all markings remain legible after assembly - move or abbreviate as needed. f For critical signals, consider redundant markings on both top and bottom, or on nearby copper. 7. Review in 3D and with printed overlays: f Use the CAD tool's 3D viewer or a printed overlay to verify all markings are visible and clear from the top, bottom, and after assembly. f If possible, review with assembly and test teams for usability feedback. Common Pitfalls, Their Impact, and How to Avoid Them Common Pitfall How to Avoid it Silkscreen on solde- rable pads or vias Leads to solderability defects or tombstoning – Set DFF clearance rules for silkscreen to copper pads/vias. Illegible or missing designators Makes debugging and assembly slow and error-prone – Place designators near their parts and do not place designators under- neath components. Unmarked polarity or orientation Can cause reversed part placement and field failures – Maintain consistent orien- tation, i.e., left-to-right. Crowding or overlap on dense boards Results in messy, useless markings – Prioritize critical markings, use abbrevia- tions, and provide detailed assembly drawings for reference.