Issue link: https://resources.pcb.cadence.com/i/1541046
9. Prioritizing Placement of Fixed and Critical Components How To Implement 1. Identify all fixed and critical placement items: f Mechanically locked: Edge connectors, mounting holes, displays, switches, LEDs, antennas, heatsinks, and panel-interfacing components. f Electrically critical: Main ICs (MCUs, FPGAs, DDR/SDRAM, RF transceivers), clock generators, analog frontends, power converters, sensitive analog or sensor inputs. f Thermally critical: Parts requiring heat sinks or airflow; high-power devices; large exposed pads needing thermal relief. 2. Place and lock mechanically constrained components first: f Align connectors and panel I/O with their cutouts or external mating positions. Use the "lock" or "fixed" status in your CAD tool to prevent accidental movement. f Place mounting holes, fiducials, and critical slots; confirm these features remain visible and unobstructed after full placement. 3. Place primary ICs and high-pin-count devices f Position MCUs, FPGAs, processors, and memory ICs to allow the shortest possible traces for critical buses (DDR, QSPI, parallel memory) and clocks. f Place power management ICs close to their loads and keep high-frequency regulators away from sensitive analog. f For high-pin-count parts (BGAs, FPGAs), allow enough escape/ fanout room and plan for decoupling on the same side. 4. Arrange supporting components for optimal signal/power paths f Cluster the key passives (decoupling caps, crystal loads, termination resistors) directly adjacent to their associated pins. Short loops reduce inductance and noise. f For clock circuits, place the oscillator/crystal and loading caps within a few millimeters of the input pins, keeping paths direct and shielded by ground. 5. Maintain clear routing corridors: f Leave open "streets" between blocks for critical buses, high-speed lanes, or power planes - avoid trapping these nets behind a wall of passives or connectors. f Visualize the "ratsnest" or connection lines and ensure the most direct paths are available for timing-sensitive nets. 6. Consider assembly and rework access: f Ensure tall parts don't block access to critical devices or mounting hardware. f Reserve room around BGA/QFN for rework nozzles and probing. 7. Review and refine placement iteratively: f After initial critical placement, review with your team (mechanical, SI/PI, assembly) and make adjustments for airflow, cooling, EMI zones, and functional grouping. f Only after critical and fixed items are placed and locked should you move on to secondary/support component placement and begin routing. Common Pitfalls, Their Impact, and How to Avoid Them Common Pitfall How to Avoid it Placing passives and "fill" parts first This blocks key routing channels and leads to via forests and layer ballooning – Prioritize placement based on function and physical constraints. Place major components first (connectors, CPUs, BGAs, high-speed interfaces, power circuits, etc). Ignoring mechanical fit or panel alignment Connectors or switches that are off by even 1 mm can block mating or user operation – Ask the mechanical team for 3D STEP files, so you can visualize and run clearance and fit checks for your product. Leaving too little space for fanout Tight clustering of BGAs/FPGAs without an escape room can make routing impossible – Reserve breakout channels and dedicated layers for escapes. Poor thermal planning High-power parts stranded away from heat sinks or airflow zones will fail to meet thermal specs – Identify high-power parts early. Add thermal vias, copper pours, and keepouts around hot zones.