Cadence PCB Best Practices

Embedded Component Design Embedded Component Design October 2019 21 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. Note: Not all vendors support merged or super cavities.It is recommended to verify fabricator's process before using cavities. ■ Placebound to via keepout expansion: (#3) Creates an extended via keepout area about the Placebound geometry. Follow the guidelines recommended by fabricator. ■ Package to Cavity:(#4) This parameter is actually a constraint and defines the clearance from the edge of the placebound shape to the cavity outline.

• Cover
• Contents
• Embedded Component Design
• Introduction
• Licensing
• Terminology
• Front to Back Flow Considerations
• Drawing-Level Property Alternative
• Applying a Drawing-level Property
• Property List
• PCB Library Considerations
• Embedded Layer Setup
• Summary
• Adding Embedded Properties
• Embedded Component Parameters
• Direct Attach Method
• Indirect Attach Method
• Embedded Component Constraints
• Summary
• Embedded Geometry Subclasses
• Placement Applications
• Interactive Placement
• Quickplace
• Placement Edit Application Mode
• Cavities
• Reports
• Manufacturing Output
• SKILL