PCB design software relies heavily on design rules to ensure a PCB layout is manufacturable and functional. Sometimes, you will need to set up length matching constraints on high-speed nets that include a termination component at the one end of the net. When there is a terminating component, such as in fly-by topology or bus topology, you may need to include the branch with the terminating component in your length matching calculation.
In OrCAD, there are tools you can use to distinguish between length matching along the main routing branch, and between the entirety of a route defined with component pins as endpoints. This is done in the Allegro Constraints Manager, which is where the designer can define physical and electrical constraints that are required for maintaining impedance and ensuring length matching.
Once the constraints are set up correctly, you will see a DRC error whenever length matching constraints are violated. This can be done easily in the Constraints Manager window. We’ll show you how it all works in this article.
How Length Tuning is Verified in OrCAD
Length tuning is used in high-speed interfaces in order two keep signals synchronized in time. There are few common instances where length matching must be enforced on a PCB to ensure high-speed interfaces are functional:
- Between two tracks in a differential pair
- Between a group of single-ended traces
- Between a group of differential pairs
- Between multiple traces and/or pairs in a large parallel bus
Option 1 is required in serial differential interfaces where two traces are used, the most common of which is LVDS. Options 2-4 are used in more specialized interfaces, such as MIPI lanes and DDR.
The equation that is used to verify length matching is quite simple and is related to the propagation velocity for signals on a PCB. The formula relating a length matching and propagation velocity is:
In this example, ΔT is the allowed timing mismatch between your signals. For a differential pair, this value could be found in a datasheet, or it could be taken as a fraction of the signal’s rise time. For parallel buses, there will be some timing mismatch allowance in the interface specification.
In the determination of length matching for a bus or a simple pin pair, you can use either the length mismatch or timing mismatch as a constraint target. Both options can be defined in the Constraints Manager window, which is accessed in the OrCAD PCB Editor. Implementing this across individual differential pairs, between multiple differential pairs, or between a large bus requires using two possible options in the Constraints Manager.
Matching Between Traces in a Differential Pair
Differential interfaces function by ensuring two signals in the pair are crossing at the same instant at the differential receiver. To ensure the routing tools in OrCAD can apply a length limitation violation flag in the DRC system, users must define differential nets by creating a Differential Pair in the Constraints Manager:
- Create a physical constraint set for your target impedance (if specified)
- Select the two sides of the differential net (positive and negative), and create a differential pair
- Select the new differential pair and apply the physical constraint from #1 to set the impedance
- Set a Static Phase value that defines the length mismatch between the differential pair
The Static Phase created in Step 4 will contain the length mismatch allowance between the two traces in the pair.
To create a differential pair, navigate to the net names that will be converted into a differential pair. Select the two net names, right click, and select Create → Differential pair… This will bring up a sub-dialog where the pair can be created and a name can be assigned.
Differential pair creation in the Constraints Manager window.
Once this is created, it can be viewed and tolerances assigned in the Net → Routing → Differential Pair area on the left panel. The length mismatch can be defined in the Static Phase → Tolerance. You could also set this as a percentage or as a time value. The example below shows a 5 mil tolerance applied to the newly created differential pair. To verify constraints are satisfied, right click on the net and select Analyze; violations will appear in red text.
View and analyze differential pair length tuning tolerance in OrCAD.
Matching Across Nets With a Match Group
When you have single-ended or differential nets, and the nets are directly routed between two component pins, you can verify matching across multiple nets by simply creating a Match Group. The Match Group verifies that a constraint is met between all pairs in a group relative to a single target. This is the fastest way to enforce length matching across a group nets simultaneously.
To create a Match Group, navigate to the group of nets where you want length matching, select these, right click, and select Create → Match Group.
This Match Group selection will apply length matching across this entire group of nets.
When a match group is created from a net name, it will include all pins along the route in the group for matching. Therefore, you should only use this if you need to apply length tuning along the entire physical copper in the layout, and not just a section between two specific pins.
Typically, a single constraint value is entered in the Delta:Tolerance, and this will apply to all nets in the match group. Constraints can also be set on a net-by-net basis, so individual nets can have tighter or looser tolerances within the match group if needed. To set a tolerance for a single net, select that net name and enter the desired mismatch range in the Delta:Tolerance cell.
Use Pin Pairs For Entire Route Verification
When some additional pins or components appear on the net, a different type of matching condition needs to be created. Instead of immediately creating a Match Group, we first need to create a Pin Pair for the nets being matched.
For example, if you have DC or AC coupling, a termination network for specialty logic, or termination applied for a specific topology, you would want to use a Pin Pair to setup a constraint for length matching. If you were to just select the differential or single-ended net name, you would be creating a matching condition for the entirety of the net, which might include a portion of the net that is not critical to timing of signals along the route. This would apply in, for example, the case shown below with an array of termination resistors.
In this topology, termination for the RAM is routed to one of the resistor arrays. The route over to the array can be included or exempted from the length tuning calculation. In our case, we only want to consider the section of the route that exists directly from the main processor to the DDR RAM chip. Therefore, we use only the pins on the processor and the endpoints to define the target length.
To do this, we need to create a Pin Pair object inside the Constraints Manager. To do this, navigate to the net name that requires matching. Right click on the net name, and select Create → Pin Pair.
From here, the Constraints Manager will open a window that lists all component pins that are present on the net. From inside this window, you need to select the pair of pins that will define the endpoints for a length matching determination. In this example, we want to match between U4 (Pin Y18) and U5 (Pin L3).
Once you click OK, the Pin Pair will be created for this component. If you have created multiple Pin Pairs, a group of these Pin Pairs can be added to a Match Group, just like you would add a group of nets. In this case, make sure you only select the pin pairs you want to match, do not select the net names when creating a match group.
Adding these Pin Pairs to a Match Group will enforce length tuning only between components U4 and U5, and it will exclude all other pins that might appear in these nets.
Once added to the Match Group, navigate to that Match Group and apply tolerances as you would normally.
Mix of Single-Ended and Differential Nets
What do we do if we have length matching constraints between both differential pairs and single-ended interfaces? This is how DDR length matching constraints are implemented with respect to the reference clock in the bus. The clock needs to also be matched to the single-ended lines in the bus so that data and memory can be queried from memory in each clock cycle.
To implement this kind of matching in OrCAD, you can create a matched group using the Pin Pairs created above, and then create a separate Differential Pair definition for the differential portion of the bus. You can then select this mix of nets (your single-ended nets and your differential nets), and then you can add these to a Match Group. See the example below.
This Match Group contains both single-ended traces and a differential pair (yellow box).
Once created, you can enter the required tolerance for this mixed Match Group as normal. The constraint value you enter will apply to the single-ended nets and the differential nets simultaneously. This completes the setup steps required to implement various length matching constraints in OrCAD.
Advanced designs need timing synchronization in digital interfaces and in RF systems, just as we’ve shown here. Make sure you build your systems using the best set of PCB design features in OrCAD from Cadence. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity.