Class 3 PCB Design Rules

Key Takeaways

• IPC PCB classifications and the added requirements of Class 3.

• A brief cost analysis of IPC Classes.

• The impact of Class 3 on design rules for DFM layout.

Class 3 PCB design rules involve enhanced visual inspection for defect detection

There are few things more frustrating than electronics that misbehave or refuse to work. Users expect an electronic device to power on and function flawlessly, but designers know how much work goes into ensuring even the simplest circuit is rugged and operates consistently. While it’s sometimes jokingly referred to as “black magic”, there are no secrets to circuit design. Designers need to follow layout best practices, supplement with manufacturer guidelines, and perform extensive modeling and testing to confirm the function of the design and quality of the manufactured product.

While it can be annoying when appliances or entertainment devices perform inadequately, the risk of harm to any user is exceptionally low. For devices where operational failure has the potential to be lethal, stronger safeguards must be in place to prevent interruptions to critical service. IPC has created three levels of electronics reliability, with Class 3 being the most stringent and demanding for manufacturing; to assist in design for manufacturing (DFM), the layout must incorporate Class 3 PCB design rules effectively. 

Class 3 Rule Changes From Class 1/2

IPC Classifications for Reliability

Not all electronics are designed and manufactured equally, nor should they be. IPC classification establishes standards for reliability across the many industries electronics serve, but classes need to not be overly demanding where reliability is less of a concern. 

Class 3 electronics are the upper echelon of design and manufacturing complexity, requiring development teams to fully embrace all the tools at their disposal. As yield and class are negatively correlated, designers will want to assist manufacturing as much as possible for Class 3 electronics production. Additionally, an assembly class and bare board class for the same design cannot exceed one another; designers will want to keep in mind that the synergy between fabrication and assembly will take on an even more prominent role.

What’s most immediately noticeable for Class 3 PCB design rules is the additional emphasis on optical inspection. Typically, Class 1 and Class 2 designs are more forgiving during optical inspection of defects that don’t otherwise detract from performance characteristics. This is not the case with Class 3: visual indication of defect is reason enough to fail a board. Because of the design goal for a rugged, long-lasting, and uninterruptable device, visual defects may later open the door for field failure or a reduced service life through various failure mechanisms (e.g., stressor leading to crack propagation).

Justifying Class 3 PCB Design Rules in Layout and Manufacturing

Failure criteria for Class 3 electronics during inspection and testing build off the more forgiving Class 1/2 requirements. To maximize performance and yield, designers need to not only understand what separates a pass/fail designation on a Class 3 board but also the underlying factors that cause them: 

• Annular rings - Annular rings are necessary to establish a minimum pad area around the drilled hole in every direction. Class 1 and 2 fabrications can get away with a breakout condition where the edge of the drilled hole overlaps or extends past the pad, but this is not the case for Class 3. A 50 micron/2 mil annular ring is necessary for external layer annular rings while a 25 micron/1 mil annular ring is required for internal layer annular rings, with the difference being the final plating. 
• Plating - For almost every combination of board thickness and via structure, Class 3 PCBs require additional plating for protective purposes. The thicker the plating, the better the coating of the via barrel to prevent cracks and voids that raise impedance or cause complete loss of continuity. As the via barrels are most likely to experience significant stress due to z-axis CTE mismatches, ensuring the ruggedness of the vias is paramount for high reliability. On average, this amounts to an additional 5 microns/.2 mil additional plated thickness compared to Class 1/2.
• Negative etchback - The recession of the inner layer copper from the via hole following desmearing. Normally, negative etchback is performed intentionally as the more cost-effective method of etchback, but it produces poorer connectivity, which disfavors the process for Class 3 electronics. The maximum allowable negative etchback is 13 microns/.5 mils.
• Void - Missing copper from plating represents opportunities for crack propagation and other localized stressors to reduce the overall reliability of the board. For vias where a uniform coating of copper is necessary for electrical and mechanical purposes, Class 3 does not allow for any voids during visual inspection.

Ultimately, the more demanding testing, inspection, and design of Class 3 electronics is likely to push out lead times. Designers and manufacturers should adjust turnaround times accordingly to not undermine the end product with an overly aggressive production schedule. 

Cadence Tools Are Trusted for High-Reliability Applications

Class 3 PCB design rules are more challenging for both layout and manufacturing, but they represent a high standard of quality necessary for some of the most important modern technologies. In several demanding environments like military operations, the use of these rules instills confidence in the ability of the board to perform at a high level without interruption. 

Whether they’re adhering to Class 3 IPC specifications or otherwise, design rules form the backbone of design by overseeing layout to prevent conflicts and unproducible features. The comprehensive Constraint Manager, just one of Cadence’s PCB Design and Analysis tools, supports users with customizable DFM and is fully integrated with OrCAD PCB Designer for ease of operability.

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