Printed Circuit Boards are getting to be more complex over time. With that ongoing development, high-speed interfaces become more common. Whether it is a PCIe, Ethernet, USB or memory of some kind, clock nets proliferate across the board. Those clocks have kindred spirits in nets that want to hit the receiver in conjunction with the ticking of the clock.
“Remember that 45 degree angles are nice but not necessary so long as you avoid acute angles in the routing”
Crucial parameters of a group of traces include the target length or maximum. Less is more. Most other signals on the board will switch from time to time. Meanwhile, the clock switches all the time. The clock uses the same voltage but the constant stream of “10101010101…” creates more energy fields than a seemingly random sequence of ones and zeros. These constantly shifting reactive fields of the clock nets are the reason we want to shield the clock, giving it space to do its thing.
Shorter Traces Equal Lower Electromagnetic Emissions
Circling back to less-is-more, shorter clocks have comparatively lower emissions and are less lossy. This gives rise to the notion of using the available length matching tolerance to minimize the length of the clock. This all starts by finding the longest member of the group. Look at that net and see if there are any extra bends or places where it can be shortened.
Figure 1. Image Credit: Author - Single ended with 128 lanes using 2 out of 12 layers; one of my favorite routing tasks. Due to placement, there was a lot of tuning with two more layers full of diff-pairs.
Remember that 45 degree angles are nice but not necessary so long as you avoid acute angles in the routing. Stretch that trace like a rubber band around the obstacles until it is as short as possible. Ideally, it falls to second place or further down the list as sorted by length.
Now, is there any way to make that one the second longest any shorter using the same process? Keep massaging the traces with a focus on shortening the longest ones. Once those longer traces are optimized, the ideal length of the clock can be found by subtracting the tolerance of the timing budget from the length of the longest connection.
Example: The longest trace in the group is 18.5 millimeters and the length-matching requirement is that all traces are equal to the clock plus/minus 0.5 millimeters. That indicates a clock length of 18 mm even. Why wouldn’t we just match all of the lengths exactly? That’s going beyond the spec for one thing.
The other thing is that it would compel the naturally shorter traces to grow to the full 18.5 mm rather than meandering to the point where it approaches the 18 mm of the clock minus the 0.5 mm tolerance in this example. The full range of the traces is 18.5 to 17.5 mm with the clock straddling the difference. Again, this ideal length for the clock is found by subtracting the tolerance (or most of it) from the longest trace once everything is optimized. The caveat is that any editing of the clock or the traces on the edge of the tolerance band is likely to upset the timing budget.
Figure 1. Image Credit: Author - Some situations call for outer-layer routing such as this DDR3 implementation where the microcontroller is pinned out to mostly match the memory chip.
The upside is that this uses the minimum amount of copper, every segment of which is a potential emission concern. This is the template that could use the least amount of real estate as well. That happens by getting the traces folded in a way that takes up the blank spaces in the overall maze. Once the traces meet the timing budget, it’s not hard to find a way to add a wrinkle here and take one away from the same trace elsewhere. The wrinkle that goes away becomes room for the next trace to follow the new contours. It may seem tedious but it’s one of my favorite PCB Design tasks as it rewards creativity and persistence.
Every Trace in the Group Matched As Close As Possible
There are times when the length tolerance is so small as to render these gains irrelevant. One example is EMMC where the total number of wires is six and only five of those are matched. They are very well matched and one of those occasions where I want every trace to be very tightly constrained.
Figure 2. Image Credit: Author - Another outer-layer approach driven by the series elements over a 4-layer PCB routing solution.
Making every trace the same length as the longest natural trace is the game-plan in that event. Placement becomes the critical factor so that the connections have a similar path. Signal integrity people generally prefer that the critical traces like these have all of their tolerance available meaning that you have zero or practically zero slack in the matching rules. Call it risk aversion but sometimes you only get one chance to shine for the customer.
Time Of Flight Rather Than Length Of Trace
All along, this discussion has been about the length of the traces. In absolute terms, what we’re really talking about is propagation delay. Delay is not measured in millimeters; it’s measured in milliseconds. When the tolerances get unusually thin, we want to account for the physics in play where traces on the outer layers allow data to flow faster than the traces on internal layers.
Calculating the “time of flight” involves taking the topology into account. We typically prefer the routing to go on inner layers to reduce electromagnetic interference even though the outer layers are faster in terms of propagation delay. This is slightly more complicated than just measuring the trace lengths. Limiting the exposed traces to fan-out areas is a simple way to manage the disparity.