Custom ASIC design is no longer just the domain of semiconductor manufacturers and specialty design houses. Some of the biggest names in technology, some of which have nothing to do with hardware, are assembling their own semiconductor design teams to bring chip design operations in-house. These companies then contract with a foundry to build their systems-in-package (SiPs), proprietary components that live only in the company's products.
This opens opportunities for companies to create innovative SiPs, as well as OSATs and specialized substrate design firms to build packaging for these products. By working together, these companies can integrate their IP and physical designs into high quality SiPs. Whether your company develops IP or provides component design services, here's a guide to the list of major components and peripherals needed in today's advanced SIPs.
Designing a System-in-Package Architecture
The approach to designing an SiP architecture really depends on what the SiP needs to do. SIPs today are mostly specialized processors with some built-in peripherals, with the goal being to reduce total system size and BOM count. They typically serve specific applications or purposes due to the fact that suitable components are not available from other vendors.
Overall, the use of a custom SiP or an equivalent SoC gives a design team several benefits:
Multiple chips can be consolidated into a single chip
Specialty functions can be heterogeneously integrated
It may be easier to control package performance, such as power distribution
The developed architecture can be made proprietary
There are some important pieces needed in a SoC/SiP system architecture for basic processing and communication with peripherals.
A typical block diagram is shown below. In a typical SoC, all of these pieces will generally exist on the same die. In the SiP approach, some of these blocks can exist as external dies or peripherals. In particular, sensor interfaces, an analog front-end, RF front end, and custom logic are all typically placed as peripherals on their own dice, while the main processor block and a small amount of memory are placed on the same die as a CPU.
Typical system architecture (WikiChip)
The approach shown here also extends to multi-core processors with traffic being managed by switches and routers in the package. With a multicore processor, those additional functions will be provided on-die and do not necessarily increase the package complexity. The addition of peripherals will increase the package complexity and could demand a 2D, 2.5D, or 3D approach.
Type of Packaging
With today's more advanced ASICs and processors being heterogeneously integrated, the designer’s responsibility is to choose the type of packaging that will best suit the component. Depending on the type of package and fabrication capabilities available from your substrate manufacturer, some package types may not be available. Some 3D-stacked packages require assistance from a foundry in order to successfully fabricate the component and prove reliability in a package.
As of 2023, more packaging manufacturing capacity is becoming available outside of China, Japan, and Taiwan. While not all 3D-stacked packaging approaches may be available, the easiest to approach may be 2D or 2.5D packaging, such as on an interposer or directly on a substrate. If much greater integration is needed, such as in an application processor with a lot of stacked memory, this would justify a 3D-stacked package.
2D/2.5D package architecture options from the 2019 Heterogeneous Integration Roadmap (IEEE EPS)
The 2D and 2.5D packaging styles are typically the easiest approaches, especially if the interposer can be eliminated. Routing in the package substrate is very similar to HDI PCB design, where a redistribution layer and internal channels span from the semiconductors down to a ball out on the bottom of the package. With an interposer, there is a separate step needed in fabrication and in design in order to complete the package. This increases design complexity and overall costs for the component.
Integration of Chiplets
This approach to ASIC or unique processor design can't work without access to chiplets put into the package. The market for chiplets is slowly growing and this gives more design teams access to unique functionality to integrate into their component packaging.
Currently, chiplets are not being sold on the open market as commercial products that would be procured from a distributor. There are some bare dice being sold, such as for RF components, but this is the exception rather than the norm. Normally, integration requires development or production of a custom chiplet from a foundry, or licensing of IP from a vendor. Once that data is obtained, it is straightforward to design a package to bring signals from chiplets onto a ballout and into a PCB.
Companies that build devices requiring custom ASICs need a suite of design tools that support advanced packages. Multi-disciplined design teams rely on the best set of PCB design features in Allegro X from Cadence. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity.