Manufacturing processes naturally provide a source of heat-related aging of materials.
How heat-related failures may be commonly expressed.
Mitigating failures due to heat with intentional manufacturing and design choices.
Failure modes listings are populated with thermal-related issues
Despite the best efforts of engineers to infuse reliability into electronics, Father Time is undefeated. In time, all boards succumb to the effects of age-related wear and tear that eventually leads to unavoidable failure. These changes arise due to the enthalpy of the system bringing about an irreversible disorder that results in changes to the underlying material properties of the device. Entropy is directly proportional to heat transfer between different areas of the board, so it stands to reason that mitigating heat transfer wherever and whenever possible is a strong bet to help reduce the incidence of failure as well as its mean time to the occurrence.
Though there exist many additional avenues, early failure mode lists are populated with examples of excessive heat build-up that leads to material degradation and poor performance. Designers should be cognizant not only of how and where these failures manifest, but also the underlying manufacturing processes that function as propagating events.
Manufacturing Products and Processes That Can Contribute to Failure
Heat is almost universally the cause of eventual failure in PCBs. Whether this comes about from overstressing conditions, where the materials and layout are unable to handle a large heat flux, or the more subtle degradation of thermal cycling, heat is a constant threat to the short- and long-term reliability of board features and components. Although failure events are unwelcome, they are a learning opportunity for root cause analysis to bolster future processes, revisions, and products. These are but a few of the many complex interactions occurring at any time during board manufacturing and operation that imperil reliability:
- Sequential lamination - Lamination is the process by which separate layers of the board are joined together by high heat and pressure. For complex via structures or other features of the board that require additional lamination steps, the board is subject to these material stressors multiple times. Unlike in single-step lamination where the board material is homogenous (though not isotropic), some plating will take place before later lamination steps. The coefficient of thermal expansion, or CTE, is affected by the anisotropy and nonhomogeneity, which causes the prepreg to expand many times faster in the z-axis than the copper-plated via holes and can create cracks in the barrel. Additionally, high-stress areas can arise that are distributed around the pads of buried vias and any microvias connected to them, which can lead to opens and delamination.
- Solder profile - RoHS material standards may be nothing new at this point, but the significance of the material properties’ alterations cannot be understated. The reflow temperature of eutectic tin-lead solder is significantly lower than that of lead-free solders. The latter solder mixtures suffer from either a higher melting point coming much closer to the lower limit of the common temperature or potential oxidation issues that reduce the long-term stability of the bond.
- Thermal cycling - Depending on the industry, boards are rated for differing amounts of expected thermal cycles to failure. Components may experience cycles asymmetrically, such as in touchscreens that experience different loading or consistent “hot spots” due to more concentrated usage. Solder bonds experience stressing after the solidification of the bond, which is relieved by an increase in grain size that accelerates with higher temperatures. The growth of the grains creates voids at the grain boundaries, which propagate, join, and form cracks.
Failure Modes Listings Induced by Thermal Stress (And More)
With an idea of the causes of failures, designers can collaborate with manufacturers to prevent some common-occurring issues. While rework is possible in most cases when these defects manifest early in the production cycle, the more nefarious presentation is their formation past the respective processing stage or well into a board’s field life:
- Plated through hole failure - Along with aforementioned issues caused by z-axis CTE mismatches creating cracks in the via barrel, cracks can form in the foil or at the corners of the intersection of the barrel with the top or bottom layers. Corner cracks may also manifest due to poor quality or quantity of copper plating. Separation of the internal layer with the via barrel can also form due to debris or smear left behind by drilling that is not cleaned up but can also come about from stress related to larger drilled holes and thicker boards. Coupons undergo thermal stress tests, which may include cooling cycles depending on the board’s potential field conditions, to detect and remedy defects in the drilling/plating process.
- Delamination - Visually, delamination appears as a burgeoning or blistering of the material as it separates due to a combination of heat and moisture content. Preventing delamination requires considerations from both the materials and enclosure. The two metrics most commonly used to evaluate the durability of a laminate are the thermal decomposition temperature and the time to delamination. The decomposition temperature occurs when a laminate experiences a 5% reduction in mass due to physical loss, though the laminate experiences extensive damage before reaching this point. Time to delamination, meanwhile, evaluates failure due to constant thermal loading.
- Conductive anode filament (CAF) - Current flows from anode to cathode, and over time, the material tends to extend in the direction of this flow along the glass fiber weave due to the effects of electromigration. These filament growths lead to a loss in resistance, ultimately creating shorts. Much like delamination, temperature and moisture content are driving contributors, but greater potential between the two poles is also a factor. In terms of cost-effectiveness and ease of implementation, the best method to prevent CAF is to minimize adjacency between high-bias pins (such as power and ground) and maximize the physical gap between them.
Ward Off DFM Failures With Analysis and Simulation Tools
Failure modes listings can include far more faults than what has been presented here; PCB manufacturing is an exceptionally difficult and involved process, especially when designers and manufacturers push the feasibility to the limits of technical realizability. Design teams should consider all potential avenues of material degradation and consider incorporating “safety factor-esque” supplementation of features wherever possible to prevent the ingress of wear into the board.
Simulation provides an excellent avenue for determining various long-term performance aspects of a board, and Cadence’s suite of PCB design and analysis software offers a staggering amount of options for all levels of PCB development. Alongside the powerful yet easy-to-use OrCAD PCB designer, development times can be accelerated without a loss of fidelity in quality.
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