Types of HDLs Explained

Key Takeaways

• Learn about hardware description languages.

• Learn more about the different types of hardware description languages.

• Languages like Chisel and MyHDL offer high-level abstractions for productivity in FPGA and ASIC design, bridging hardware and software.

• Cadence's offerings for FPGA  solutions.

When we think of programming languages, we often think of software languages, like C or Python, which are used to write software that runs on pre-existing hardware without directly altering or defining the hardware's underlying structure. 

However, there are also various types of HDLs—or hardware description languages—used to describe the behavioral characteristics of digital logic circuits. We utilize HDLs for designing processors, motherboards, CPUs (important to note: code defining the CPU, not the code running on the CPU), and various other digital circuitry.

• Hardware Description Languages describe the behavior and structure of digital circuits at a low level, allowing you to design and simulate how actual gates, flip-flops, and other components 

• With software languages, you are defining algorithms, data manipulation, and control flows that instruct processors how to execute tasks, manage memory, and interact with input/output devices. The underlying hardware architecture remains fixed, and the software simply leverages its resources (such as registers, memory, and instruction sets) to perform computations.

Two of these field-specific (hardware description) languages are VHDL and Verilog. Both are considered traditional general-purpose digital design languages, each with subtle differences and advantages over the other. Traditional HDLs like VHDL and Verilog focus on low-level hardware description, providing detailed, gate-level control and closely mirroring the physical hardware design. In contrast, modern HDLs such as Chisel and MyHDL emphasize high-level abstractions, enabling designers to use advanced programming constructs, which streamline complex hardware design and integrate more easily with software development processes.

Three Most Popular Traditional Types of HDL Languages Compared

Compared to the original Verilog, one of the operational advantages of VHDL is its full-type system. This system affords designers the ability to write much more structured code, and this is particularly useful if declaring record types. There’s also SystemVerilog, which aims to improve on Verilog. Below we’ve summarized them into a table

What Is VHDL?

Very High-Speed Integrated Circuit Hardware Description Language (VHDL) is one of the major types of HDLs . It is utilized in electronic design automation to express mixed-signal and digital systems, such as ICs (integrated circuits) and FPGA (field-programmable gate arrays). We can also use VHDL as a general-purpose parallel programming language.

We utilize VHDL to write text models that describe or express logic circuits. If the text model is part of the logic design, the model is processed by a synthesis program. The next step in the process incorporates a simulation program to test the logic design. During this step, we utilize the simulation models to characterize the logic circuits that interface to the design. We refer to this collection of simulation models as a testbench.

Typically, a VHDL simulator is an event-driven simulator which means that we add each transaction to an event queue for a particular scheduled time. For example, if a signal assignment occurs after one nanosecond, we add the event to the queue as time + 1ns. Although a zero delay is allowed, it still must be scheduled, and for these scenarios we utilize a Delta delay (infinitely small time step). 

VHDL Functionality

These simulations alternate between two modes:

• Statement Execution: In this mode, the triggered statements are evaluated. 

• Event Processing: During this mode, the events in the queue are processed.

Though there is an inherent similarity in hardware designs, VHDL has processes that can make the necessary accommodations. 

The Advantages of VHDL

The critical advantage of VHDL, with regard to system design utilization, is that it permits the behavior of the essential system to be verified and modeled in advance of the synthesis tools translation of the design into actual gates and wires (hardware). VHDL projects are also portable, which means that you can generate a project for one element base and then port it on another element base, such as VLSI, with a variety of technologies.

Using VHDL affords the user concurrent system descriptions. VHDL is a dataflow language, which means it can simultaneously consider every statement for execution. This is in direct contrast to procedural computing languages like C, assembly code, and BASIC. Each of these languages runs a sequence of statements, both sequentially and a single instruction at a time.

One of VHDL's more advantageous benefits is that its projects are multipurpose; you create the project once, and you can utilize the calculation block in various other projects. This means you can make changes to parameters, element base, memory size, block composition, interconnection structure, and capacity.

All About Verilog

As I am sure you are aware, Verilog is also a Hardware Description Language. It employs a textual format to describe electronic systems and circuits. In the area of electronic design, we apply Verilog for verification via simulation for testability analysis, fault grading, logic synthesis, and timing analysis.

Verilog is also more compact since the language is more of an actual hardware modeling language. As a result, you typically write fewer lines of code, and it elicits a comparison to the C language. However, Verilog has a superior grasp on hardware modeling as well as a lower level of programming constructs. Verilog is not as wordy as VHDL, which accounts for its compact nature. Although VHDL and Verilog are similar, their differences tend to outweigh their similarities.

Verilog HDL is an IEEE standard (IEEE 1364). It received its first publication in 1995, with a subsequent revision in 2001. 

What is SystemVerilog?

SystemVerilog, which is the 2005 revision of Verilog, is the latest publication of the standard. We call the IEEE Verilog standard document the LRM (Language Reference Manual). Currently, the IEEE 1364 standard defines the PLI (Programming Language Interface).

In general, Verilog lacks the advanced constructs needed for large-scale system verification. SystemVerilog is an extension of Verilog, and was developed to address these limitations by adding features for more complex design and verification tasks.

It includes object-oriented programming (OOP) concepts, enhanced data types, assertions, and interfaces for better abstraction and reusability. SystemVerilog also integrates verification constructs like random stimulus generation and functional coverage, which streamline the testing and debugging of hardware designs. As a result, SystemVerilog is preferred in modern, large-scale projects, especially for verification environments, whereas Verilog is typically used for simpler, smaller-scale designs.

Note: The PLI is a collective of software routines that allows a bidirectional interface between other languages such as C and Verilog.

Key Modern HDLs

Recent modern types of HDLs all share a common theme of abstracting away traditional HDL syntax by using higher-level programming languages and constructs. These languages aim to simplify hardware design by leveraging the power of modern programming paradigms like object-oriented programming, functional programming, and high-level abstractions. 

This allows designers to focus more on the architecture and functionality of hardware systems, rather than the intricate details of low-level hardware description. They support agile hardware development, advanced verification, and code reusability, making them more accessible for software-oriented engineers and well-suited to dynamic, large-scale projects.

Key Modern Types of HDLs

1. Chisel: Based on Scala. Provides powerful hardware generation capabilities with functional programming.

• Ideal for creating parameterized hardware, such as RISC-V cores.

• Based on Python. Allows high-level hardware description and generates traditional HDLs (Verilog/VHDL). Great for rapid prototyping and easier integration with software tools.

• Offers strong guarantees on correctness, making it useful for safety-critical systems.

• Designed for productivity and optimization in FPGA and ASIC designs.

• Suited for FPGA programming and open-source hardware projects, enabling a more agile development process.