All of the little details were squared up when the check-plots came out for "final" review. Those same preliminary files were shared with the fab and assembly units and, of course, the vendors have comments on how you can make it easier for them. Even though it was the final PCB review, someone, usually someone with vast knowledge and, importantly, clout, will open up the schematic or offer an improvement. While this idea was quite simple to hook up in abstract view of the schematic, it usually ends up being a little more interesting to pull off on PCB.
By that, I mean that we might engage in the design work where edits on one layer could impact other layers in unintended ways. For sure, we always browse the individual layers but usually at a full zoom where the details can escape notice. The one thing that brings peace of mind, in this case, is reliance on the CAD tools to spot problems. Lucky for us, those tools have gotten much better across the board. (pun intended) Life, especially for an analog designer, was pretty rough back in the earlier times.
Image credit: Author - things that used to break the design rules can be safely implemented with modern tools.
Let's say I want to make a line on the outer layer of a board that is a shunt inductor at a higher frequency while also being a DC short from the RF line to the ground plane. It is a transmission line with a branch to ground. There would have been no way to do that without leaving a design rule violation behind. Even the notion of officially ignoring the DRC flag was not on the table. Copper was dumb and needed to be poked and prodded with skill and/or luck to achieve anything resembling cool.
Today, there is so much more we can do to ensure and verify a good design. The advancements in the tools allow for more seamless integration with SI/PI simulations that should always accompany an aggressive layout. Fit checks with 3D accuracy are a product of simple exports that help the physical design team visualize and quantify the board within the system. All of these models move the design forward without intermediate tape-outs. Then, after we have learned what we can and adjusted to the data, we stand a better chance to create a working PCB.
Still, with all of the technology, the human element is always in play. We're busy, distracted, multi-tasking marvels. All too frequently, we’re down to the 11th hour before we can produce our deliverables. The late adjustments are not usually that profound, but there are exceptions. A simple net-name change along the power rail can leave legitimate looking shapes that serve no purpose or are spread out beyond the new requirements. I call them artifacts that must be rooted out.
The guru (small g) mind trick for this is to go old-school and print all of your artwork layers on the big format. The rouge reference designator or lost via will suddenly jump out at you. Walking into the last-minute design review with a copy or two of the check-plots will give you something to share while setting up the conference room. The point of this exercise is to make sure we closed on any outstanding items. The reality is that sometimes, we're on the hook to edit a few things and turn around some artwork that same day.
The Chrome OS Hardware team at Google wanted to build the ultimate Chromebook and released the Pixel, mostly for developers but a few civilians also paid Mac money for a laptop. The 2013 version was upgraded in 2015 with two USB type C ports; one on either side. That was the one I designed. Somewhere in the penultimate cycle, we introduced a new audio CODEC to the layout. It was one of many improvements to keep the Pixel on the cutting edge. Lots of features meant that lots of engineers were boarding planes for somewhere in China to do the bring-up. Not just flights, but hotels, meals, ground transportation, lab space, equipment, meeting rooms booked for dozens of Googlers. No pressure!
They were not over there for very long before finding out that CODEC was utterly non-functional. Every pin on it, eighty-some pins on a 0.4 millimeter grid were backward. The librarian read the ball map as shown from the bottom while building it looking through the top. I didn't check the footprint or cajole anyone else to do it so we had a laptop that was great for watching silent movies. The very next iteration of the main logic board was for mass production, so you can bet that we made sure the audio engineer had something to do on the next trip to China. Fortunately, sound recreation is a pretty well understood discipline.
Photo credit: Author - Google’s first in-house Chromebook was a dandy.
Hardware design certainly has an effect on how well the software operates and it works the other way around too. Our coding heroes can make up for poorly matched byte lanes or slow the entire system down rather than let the devices cook themselves. Poor design on either side hurts both. A little understanding for the other teams' difficulties will help us bear the pain of eleventh-hour surprises. Yes, we can!
Generally speaking, the schedule rules all, and we do everything we can before the tape-out date arrives. Occasionally, show-stopper issues crop up and we enter the zone of day-to-day slippage. Each day the question is unanswered or the problem unsolved is another day late. The tension mounts and is eventually released as the team pulls it all together. That is when preparation meets opportunity. In the interim, we can revisit the DFM report for any items we thought would take too long to implement but might work out with the extended schedule. More check-plots or status reports to help the team understand the situation can't hurt.
A board that is cool under pressure relies on a designer that is also ready for the bright lights. I had an Engineering Manage tell me that the EE's will be antsy while their job is delayed but will get over it soon after they get the shiny new PCB into the lab. He went on to add that they will remember if the board has a critical failure owing to a design mistake. That part sticks. You do not want to fall right back into crisis mode after putting so much effort into the project. That is the reason why every last-minute task needs a careful look at any affected layers before moving on including non-metal layers such as keep-out layers in addition to silk and mask.
All of this to say that tape-out day can be stressful, and can turn into tape-out week. There will always be that nagging doubt that something is less than perfect. I always get one last look at the data when the ODB++ translator's viewer shows the artwork. It likes to change solid blocks of silkscreen ink into outlines if the settings are not right. It is really easy to run it again if a little defect surfaces.
At some point, you just have to let go. For the 2015 Pixel laptop, that mass production release came at 7:30 PM on December 24th, 2014. We put a bunch of people on a plane to China. A few months later, the announcement came out with the specs including the two USB type-C connectors, one on either side.
Image credit: Author - that little LED trick was just because we could.
That same week, Apple had released their single-port mac with a bit of negative buzz surrounding what was, at that time, an exotic connector while Google could also boast a pair of traditional USB ports, an SD card slot and, yes, a headphone jack. Ultimately, the Pixel was not a commercial success. I confess that my wife has one, but I'm writing this on a touch-bar Mac with no less than four USB type C sockets AND the headphone jack.
Every tape-out day is a gamble, and quite often, the stakes are high. The price of boards and components is not low but the time lost on a flop is immeasurable and unrecoverable. Hitting the market window and moving on to the next opportunity is part of our job description. Executing on the first one enables the second one. On the other hand, missing the schedule on one design often causes a ripple effect on the next big thing. Weeks or even months of work are distilled into a bunch of ones and zeros. Click that send button and put some people on a plane. It's what we do. Happy Tape-out Day.
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