Today’s modern electronic designs require ever more functionality and performance to meet consumer demand. These requirements make scaling traditional, flat, 2D-ICs very challenging. With the recent introduction of 3D-ICs into the electronic design industry, IC vendors need to optimize the performance and cost of their devices while also taking advantage of the ability to combine heterogenous technologies and nodes into a single package. And while this greatly advances IC technology, 3D-IC design brings about its own unique challenges and complexities, a major one of which is thermal management.
What’s more, thermal integrity of both 2.5D and 3D electronic designs are further exacerbated by increases in power density and thermal resistance of the dielectric layers between the active devices. Consequently, thermal management of 3D-ICs is quickly becoming a widely recognized technical design challenge for successful and widespread implementation of this technology.
To overcome the issues associated with thermal management, a thermal solution that can handle the complexity of the entire design efficiently and without any simplification is necessary. Due to nature of 3D-ICs, the typical point tool approach that dissects the design space into subsections cannot adequately address this need. This approach also creates longer turnaround time, which can impact critical decision making to optimize design performance. A more effective solution is to utilize a solver that not only has the capacity to import the entire package, PCB, and chiplets, but also offers high performance in order to run the entire analysis in a timely manner.
Complete Electrothermal Co-Simulation
To this point, Cadence introduced the Celsius™ Thermal Solver, a unique technology that is integrated with both IC and package design tools such as the Innovus™ Implementation System, Allegro®, and Voltus™ IC Power Integrity Solution. The Celsius Thermal Solver is the first complete electrothermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures.
By combining finite element analysis (FEA) for solid structures with computational fluid dynamics (CFD) for fluids, the Celsius Thermal Solver enables complete system analysis in a single tool. When using the Celsius Thermal Solver for PCB and IC packaging, engineering teams can combine electrical and thermal analysis and simulate the flow of both current and heat for a more accurate system-level thermal simulation than legacy tools. In addition, the software performs both static (steady-state) and dynamic (transient) electrical-thermal co-simulations based on the actual flow of electrical power in advanced 3D structures, providing visibility into real-world system behavior.
Based on a production-proven, massively parallel architecture, the Celsius solver also provides end-to-end capabilities for both in-design and signoff methodologies and delivers up to 10X faster performance than legacy solutions without sacrificing accuracy. These unique capabilities enable new system analyses, design insights as well as empower electrical design teams to detect and mitigate thermal issues early in the design process—reducing electronic system development iterations and costs.
3D-IC Thermal Analysis Case Study
To illustrate, a recent customer engagement with the Celsius solver for 3D-IC thermal analysis highlights the advantages of this technology and its streamlined system design workflow methodology. As mentioned previously, one of the main hurdles in thermal management of 3D-IC is related to the capacity of the tool being used for the thermal analysis. In this particular case study, the Celsius Thermal Solver successfully performed a complete 3D-IC analysis of a package with multiple chiplets where the complete model, imported in its entirety into Celsius (inclusive of the full substrate model and detailed power maps for the chiplets) consisted of a PCB, a roughly 30x30cm square package, two main system on chips (SoC), as well as at least two dozen, actually more, chiplets on top of the two main chips.