APPLICATION NOTE
4
Note: In the attached circuit, make MAX_DELAY as root and then select MAX_DELAY-MAX_DELAY as
simulation profile
Figure 3: Circuit Diagram with Min and Max Delay
Figure 4: Simulation results with Min and Max Delay
Design with Worst-Case Timing
Digital worst-case timing simulation is useful when timing of the signals are critical to the proper operation
of Design. In a simple timing simulation (using one of MIN, TYP, or MAX delays), signal propagation
through digital devices is normally represented as "instantaneous" transitions, such as those in the
examples above.
During worst-case timing simulation, the effects of individual component delay ranges are propagated
throughout the circuit. The "transitions" take both the MIN as well as the MAX delay characteristics of their
