APPLICATION NOTE
3
Design with Minimum Delay
Figure 1 below shows the Circuit Diagram with Logic Gates having MNTYMXDLY=1
Note: In the attached circuit, make MIN_DELAY as root and select MIN_DELAY-tran as the simulation
profile
Design with Minimum and Maximum Delay
Correct behavior is indeed observed at both extremes of the propagation delay range. Circuit Diagram
shown in Figure 3 below has one of the components operating slow with maximum delay and the other
component operating fast with minimum delay.
Figure 1: Circuit Diagram with Min Delay Figure 1 Min Delay
Figure 2: Simulation results with Min Delay
