APPLICATION NOTE
6
are indigenous to circuit definition. They yield analyses that are inherently pattern- independent, and very
often pessimistic, in the sense that they tend to find more problems than will truly exist. This is due to the
fact that they do not consider the actual usage of the circuit under applied stimuli.
PSpice does not provide this type of "static" timing verification. Digital worst-case timing simulation, as
provided by PSpice, is a pattern-dependent mechanism that allows a designer to locate timing problems
subject to the constraints of specific applied stimuli.
© Copyright 2016 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, and Spectre are registered trademarks of Cadence
Design Systems, Inc. All others are properties of their respective holders.
