APPLICATION NOTE
5
propagation paths; therefore, transitions may be thought of as "regions of signal ambiguity." This is due to
the uncertainty of which delay value (MIN, MAX, or somewhere in between) actually applies to each
component used in the design. PSpice represents this type of signal ambiguity with "Rising" (R), and
"Falling" (F) logic levels.
Circuit Diagram shown in Figure 5 below has both the components operating with worst-case delay.
Note: In attached circuit, make WORSTCASE_DELAY as root and then select WORSTCASE_DELAY-
WC_DELAY as simulation profile
Figure 5: Circuit Diagram with Worst-Case Delay
Figure 6: Simulation results with Worst-Case Delay
Note that, due to the uncertainty of the arrival time of both the data and the clock signals, a warning is
generated by PSpice, and the output is marked as X' (unknown) from 54.8ns to 62ns.
Other tools called "timing verifiers" are sometimes used in the design process to identify problems that
