PSpice Application Notes

APPLICATION NOTE 2 Purpose This document explains the digital worst-case timing simulation feature, to evaluate the timing behavior of Digital and Mixed Analog/Digital designs, as a function of component propagation delay tolerances. Digital Worst-Case Timing Digital worst-case timing capability simulates all devices in the Design with the full range of MIN through MAX delays in true "worst-case" mode. Component propagation delays are usually expressed in the .model parameters associated with component types, with -MN, -TY, and -MX suffixes (e.g., TPLHMN ) representing MINimum, TYPical and MAXimum delay values. These values are obtained from the manufacturer's specification sheets for the components used in the design. In cases where some of these parameters are unspecified, PSpice can establish the missing values by extrapolation. Provided below is an example of MIN and MAX propagation delay specifications for a BUF primitive. .model T_BUF UGATE ( ; BUF timing model + TPLHMN=5ns TPLHTY=8ns TPLHMX=10ns + TPHLMN=9ns TPHLTY=10ns TPHLMX=15ns + ) PSpice has simplified the use of different timing models, using the property of MNTYMXDLY, for most families of logic. This property can be set on Parts or on the Design. The values for MNTYMXDLY are: Value Timing Models Used 0 Default for design as defined in Simulation Profile, Options Gate-level simulations 1 Minimum Delay 2 Typical Delay 3 Maximum Delay 4 Worst Case Analysis The default value of MNTYMXDLY=0 for each part, while the Timing Mode under Options>> Gate Level Simulation is Worst-Case. Digital worst-case timing simulation can suggest if the digital design would operate as expected, under the worst possible combination of component delay tolerances. In this regard, worst-case is superior to separate MIN and MAX simulations, which rely on observing circuit behavior only at the extremes of specified tolerances.

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