Issue link: https://resources.pcb.cadence.com/i/1180176
Allegro Front-to-Back User Guide Synchronizing Schematics and Boards October 2019 64 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. Need for Synchronization The primary need for synchronization is caused by changes that occur either in the board or in the schematic after the initial transfer of packaged information to the board. The changes that occur in the board after the initial transfer of packaged information from the schematic are of the following four types: 1. Component changes You may add new components in the design to handle signal integrity and electromagnetic compatibility problems. These components may include termination resistors, series or shunt buffers, and bypass capacitors. 2. Connectivity changes You may make connectivity changes to facilitate routing after the initial placement of components. Connectivity changes may be caused by pin swaps, section swaps, and reference designator (refdes) swaps. 3. Reference designator changes You may change reference designators to debug board problems. 4. Property changes You may modify certain components in the board. These modifications will cause property changes. Design Synchronization Tasks The entire Design Synchronization process can involve the following tasks: 1. Package and export the schematic design to the layout editing tool by running Packager- XL in the Forward mode. 2. Compare the schematic and layout designs. 3. Package the design for feedback by running Packager-XL in the Feedback mode. 4. Backannotate the physical connectivity changes to the schematic. 5. Backannotate the schematic based on information in the board. 6. Run the Packager utilities to complete any or all of the following steps: a. Generating the Bill of Materials