Allegro Front to Back User Guide

Allegro Front-to-Back User Guide Getting Logical Design Ready for Physical Layout October 2019 41 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. Preparing a System Capture Design for Physical Layout System Capture lets you run design rule checks (DRCs) to identify connectivity and other errors in the design. System Capture provides a standard set of DRCs, and also lets you write your own custom DRCs in the Tcl language and run the custom DRCs. DRCs, such as the property overlap DRC, are controlled by the values set for the variables in the overrides value TCL file. You can enable or disable individual DRCs. When you run DRCs, the DRC errors are reported in the Violations window. You can also set the error severity level -- Error, Warning or Information -- to be reported in the Violations window if an enabled DRC fails. For example, if you set the error severity level for the Unconnected Nets DRC as Warning, System Capture displays warning messages for each unconnected net in the Violations window. Preparing a DE-HDL Design for Physical Layout Allegro Design Entry HDL Rules Checker lets you check for violations of design-related rules in a design as well as obtain information about various aspects of your design. It includes fifteen sets of rules and design checks that let you know early in the design cycle if you are violating design rules. Using this tool, you can also check rules in logical and physical environments. These rules check for fan-in and fan-out errors, load errors, required properties and property values, unconnected elements, naming requirements, power requirements, cost requirements, and so on. The first time you run Rules Checker on your design it opens with the default settings. When you exit Rules Checker, it creates an initialization file (CheckPlus.ini) that contains the following information: ■ Last selected environment ■ Selected and deselected rules ■ Expanded and unexpanded rules Note: For detailed information about Rules Checker, refer to Allegro Design Entry HDL Rules Checker User Guide.

• Cover
• c contents - Contents
• Preface
• About the Front-to-Back Flow
• How This Book is Organized
• Creating and Managing Libraries
• Allegro Front-end Tools Libraries
• Library Structure
• Creating and Managing Libraries
• OrCAD Libraries
• Capturing Logical Design
• Creating Project Using Allegro Tools
• System Capture
• You can also perform other page manipulation operations, such as creating a new page or deleting an existing page from the Project viewer. You can drag and move the pages up and down to change their order in the Project viewer.
• Allegro Design Entry HDL
• Creating Project Using OrCAD Capture
• Creating a Schematic
• Designing Schematic Using System Capture
• Creating Schematic Using OrCAD Capture
• Capturing Logical Designs using DE-HDL
• Capturing Logical Design Constraints
• Why Constraint Manager?
• Using Constraint Manager with Design Capture Tools
• All the constraints are stored in the Constraint Manager Database (CMDB) and saved in the dictionary and constraints file designname.dcf.
• Constraints in System Capture
• Capturing Constraints in Design Entry HDL
• Capturing Constraints in OrCAD Capture
• Creating Variants of Your Design
• Managing Variants in System Capture
• Creating Variants using Variant Editor
• Getting Logical Design Ready for Physical Layout
• Preparing a System Capture Design for Physical Layout
• Preparing a DE-HDL Design for Physical Layout
• Exporting a DE-HDL Design
• Forward Mode
• Preparing an OrCAD Capture Design for Physical Layout
• Exporting an OrCAD Capture
• Annotating the Design
• Packaging Your Design (Advanced)
• Generating a Bill of Materials
• Updating the Schematic With the Changes in the Board
• Passing Properties from the Layout to Schematic
• Designing Layout
• Physical Layout using OrCAD PCB Editor
• Creating a Board Outline
• Creating Symbols and Padstacks
• Importing Logic
• Defining Layers
• Defining Constraints
• Placement
• Routing
• Design Synchronization
• Physical Layout using OrCAD Capture
• Preparing the Schematic for Layout
• Property Flow from Capture to PCB Editor
• Generating Initial Board File
• Backannotation from PCB Editor
• Running Design Rules Check - Physical Rules
• Capturing Physical Constraints
• Using Constraint Manager with PCB Editor
• Synchronizing Schematics and Boards
• Need for Synchronization
• Design Synchronization Tasks
• Feedback Mode