Issue link: https://resources.pcb.cadence.com/i/1180176
Allegro Front-to-Back User Guide October 2019 31 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. 3 Capturing Logical Design Constraints A constraint is a user-defined requirement applied to a net or pin-pair in a design. For example, you can capture a constraint to define the maximum voltage overshoot tolerated by a net and capture the minimum first switch delay for a driver-receiver pin-pair in your design. Cadence PCB design flow, provides a dedicated tool, Constraint Manager, for capturing and managing constraints. This tool is seamlessly integrated with schematic design tools as well as physical layout design tools. You can use Constraint Manager with design capture tools, Design Entry HDL or OrCAD Capture, to capture and manage constraints as you implement logic. Constraint Manager is well integrated with these tools, therefore, the changes that you make to constraint information are displayed in these tools. Similarly, the changes that you make to constraint information in these tools are displayed in Constraint Manager. Why Constraint Manager? Using Constraint Manager to capture design constraints has the following advantages: ■ It provides a spread-sheet based user interface that allows you to quickly capture, modify, and delete constraints. ■ It supports syntax checking for all constraints. ■ It supports constraint inheritance. The constraints captured on a schematic block are inherited by the design in which the block is instantiated. ■ It lets you create Electrical Constraint Sets (ECSets) - collection of electrical constraints that define a particular design requirement and assign them to objects on which you want to capture the same set of constraints. For example, you can create an ECSet to define the default timing and noise tolerance for a net. An Electrical Constraint Set applies to an