Back with more summer reading for you the PCB Layout enthusiasts around the globe. Our last topic was about getting off to a good start and touched lightly on placement aspects. We're going to get a little bit of solder paste under our fingernails this time around. Move the scenario forward a little bit. We won the contract and started up the production ramp with the common pre-production headaches. This leads to new solutions to tackle the problems we didn't know we had when we taped out at REV 1.
Image credit: The1Thing.com
Now comes REV 2 with all of the hindsight firmly in place. Just a few touch-ups. Maybe, you have heard it from people from one or more of the following groups:
Purchasing wonders if you can reduce the layer count and increase the minimum air-gap. Why are there always so many capacitors?
Failure Analysis is concerned about thermal paths and ESD containment.
From the Production floor: "How about a rectangle to locate the barcode and more board level fiducial marks spread around? Oh, and could you please move everything away from everything else, especially the tall things?" Seriously, there is value in distributing the components evenly around the board.
Rework technicians may have a slightly different interpretation of the courtyard around the microcontroller. Some of the little parts are getting in the way of the rework nozzle.
Inspection would appreciate a little more attention to the polarity marks on the board.
The test team would like to explore enhancing the In-Circuit-Test coverage plus maybe a JTAG connector or an I2C bus for a more complete picture.
We haven’t even touched on electrical and mechanical engineers who take a secret oath never to quit striving for a better mousetrap. The whole gang of downstream users have spoken, and their message is clear. On behalf of the end-user (read 'customer') we want this gadget to work, and we want to be able to repair it if it fails.
The Good Old Days
My days of earning a living with a soldering iron are, thankfully, behind me. Job hopping within that same company (Granger Associates, represent) eventually landed me a job running a receiving inspection lab.
Our division made Point-to-Multipoint radios for installation on offshore oil rigs. Nowadays? They use cell phones. Back then? Among my duties, I had to inspect the plated barrel of a random sample of vias on a random sample of boards of every lot that came in the door. Microscopes will mess with your vision as you focus up and down the via barrel searching for pinhole voids. From there, I found my calling in ECAD.
All About the Soldering
I said that to say this. You should know what all of the typical solder defects look like and you have to be able to identify the probable root causes based on visual or destructive testing. One of the most common problems on the assembly line is soldering the big ground slug under surface mount QFN, QFP (or similar rectangular) packages. It requires a perfect mix of soldering oven temperature profile and quantity/deposition of solder paste. The precise amount is relative to the smaller pads around the perimeter.
If you are lucky, the datasheet will have some guidance on the paste. If they allowed me to pick the components, all of the datasheets would have that information supported with actual test data. The first rule in the book if I’m buying parts is good footprint documentation.
Solder voids on the "e-pad" show up on an X-ray as bubbles in the wetting (good adhesion area) of the solder joint. Creating a pattern in the solder paste stencil that resembles a window frame with four or more openings reduces the amount of paste vs. a full-size opening. That is only one example.
Another common defect is solder bridging, and the solution may involve the solder mask, paste and/or metal work. Solder balls are another bad thing. They suggest that we used too much solder or that it was frying a little too fiercely in the oven. You can probably guess the root cause of solder voids. Hint: it's not always insufficient solder. Some defects like cold or disturbed solder joints are more likely to be process related. So, lucky me, I got all of that on-the-job training right before the surface mount revolution.
Image credit: NASA
Your shortcut to all of this wisdom lies in the workmanship handbooks (pdf) like the venerable IPC J-STD-001. Knowledge is power. Fixing a component problem and the PCB level is an abuse of that power. Always go back to the root library and put the update on the source of any future products that would use the same device. Footprint updates usually mean a rename or up-rev of the device file name to account for the history of whether a particular iteration of the PCB has the improvement or not. There are industries where that kind of detailed traceability is essential.
The placement (or misplacement) of those symbols is not far behind the footprint in terms of creating headaches for production. Lucky for most of us, the components are still available in the same packages that I used to solder. The main point with through-hole placement is getting the right hole size for each lead.
Image credit: PCB-3D
Hole size is critical because we want the sweet spot between large enough for easy robotic placement and small enough to get good capillary action on the pin such that solder ends up wicking into the hole. The nominal size of the hole is around ten mils over the maximum size of the pin, but it is a proportional equation with different ways to solve it. ANSI has a spec that applies to mechanical holes and the IPC, of course, has more than one way to figure out the optimum number. In the end, there are only so many actual drill sizes. Do not get hung up over a few microns.
No matter what technology is in play, a surface mount pad will always have at least three elements; the metal, the solder mask and the paste stencil. The metal and paste layers are positive layers: items drawn are seen in the artwork. The solder mask can be thought of as a negative layer since whatever is shown on the artwork is the area that is stripped away from the PCB.
Essentially, what we're doing is designing the space between the solder mask openings. These little walls of mask between the pads determine the outcome of the assembly process as much or even more than the metal pad layer. We call it a solder dam when it is substantial enough to keep the solder joints from fusing together. We call it a sliver when it is too thin to adhere to the PCB. The threshold for minimum dam width is four mils. If your CAD system has the means to check for these solder mask slivers, then that tool is your friend.
Components that are placed too close to an edge of the PCB are in danger because the edges of the board reach reflow temperature before the central area. Beyond tombstoning, some parts can be physically pulled apart when the leads go from paste to liquid to solid at different rates. This played out in real life on a wire wound inductor that was placed on the RF input. Electrically, it was a good idea. In practice, it became a latent defect. Failures that come and go are some of the hardest to troubleshoot.
Maintaining and Owning Quality
Find the problems yourself or find the job on hold when it is go-time. Imagine skipping the whole DFM cycle because you handled your business. That is something that the buyers will notice. Getting down to zero technical questions from the vendor does not take a miracle. Putting everything you have learned into the design and document package will at least minimize the schedule impact of DFX hang-ups. If you were proactive with the feedback from the first revision, the risk is lower this time around. It is your name and your reputation in the title block. Make it count.