System-level signal and power integrity help prevent mistakes when reading bits
It would be quite nice if we could rest assured that all our circuits always received 5 V when we set the power supply/power regulator to 5 V. However, this is simply not what happens in a real device. If you are working with TTL/CMOS devices that run at higher voltage and have high noise margins, you likely won’t notice any link between power integrity and signal integrity. While this might be a common occurrence in a basic electronics lab, real devices on a PCB can reveal the link between system-level signal and power integrity.
With many high gate count/pin count devices running at successively lower supply voltages (reaching down to 1.8, 1.2, or 1.0 V for specialized high speed devices), the noise margins in these systems are also lower. Similarly, the high gate counts in these devices cause them to consume much more power as they draw more current during operation. Power integrity problems due to switching that would have gone unnoticed in a slower system with higher noise margins can now cause a system to completely fail. This is due to the intimate link between signal integrity problems that are produced by power integrity problems. Let’s look at this link at the system-level and see what can be done to ensure your signals remain intact.
Linking System-level Signal and Power Integrity
Power and signal integrity are linked throughout your PCB in some important ways, all of which can be understood by looking at a typical PDN in a PCB layout. When a PDN is driven with a regulator or VRM, a driven component can cause a voltage ripple on the PDN as current is drawn into the PDN.
As this transient response propagates on a PDN, it causes the source-drain and/or gate-source voltages seen in the driving IC to fluctuate, which interferes with the equivalent RC time constant and the output signal level. This transient response is responsible for the following signal integrity problems:
Jitter: Power integrity problems can create jitter (in digital signals) or phase noise (in analog signals) in the output signal from a driver IC. This affects when the driver switches and how the long the driver takes to switch. Typical jitter values are 100 ps/mV. RMS jitter in a digital signal due to ripple on the PDN can be calculated with the equation below.
RMS jitter value due to the RMS voltage ripple on the PDN.
Noise: Power integrity problems superimpose noise on the output from a driver IC. When the driver sends a signal to a downstream component, significant noise or droop in the signal can fail to drive the downstream component directly, either because the signal level is in the undefined region or because it fluctuates between HIGH and undefined. With edge-triggered receiver components, any fluctuation on the leading edge of a signal may not trigger the downstream gate correctly, if at all.
Both problems are accompanied by signal distortion along an interconnect. Your PCB substrate and trace geometry cause signal distortion, which is accompanied by signal distortion due to parasitics in chip packaging and connectors. This heavily band-limits signals collected by gates in the receiver and causes the eye diagram for the system to close (see below).
Amplitude noise and jitter as a signal travels between a driver and receiver
When one component switches and draws a large transient current into the PDN from the regulator, the resulting voltage ripple is seen by all other components on the PDN. This can arise due to crosstalk (in a star configuration) or directly due to a shared PDN connection (bus or multipoint topologies). This can cause signal integrity problems to propagate throughout the system, not just in a single switching component.
Note that we’ve discussed ICs for the moment, but the same power problems can produce fluctuations in the signal level and jitter in the system clock. Highly stable reference clocks are more resistant to power fluctuations. Any jitter in the clock output will interfere with the operation of the gates it is used to control, particularly edge-triggered components. This should illustrate the need to control skew throughout your board. In systems involving ultra-accurate time-to-digital measurements (LIDAR is a perfect example), you need to lock your relevant clock frequencies with your ADC/time-to-digital converter using a PLL.
We’ve discussed these layout choices in a variety of contexts elsewhere on this blog, but we’ll try to synthesize the important points in a general sense here. Because the link between signal integrity, power integrity, and EMI is unavoidable in your PCB, ensuring power integrity in your board requires designing the right stackup design. This is arguably the most important point to consider when designing a board for power integrity, especially in devices that run at low levels with high pin count.
The goal is to reduce the PDN impedance to as low as possible. If you are using components with 1.2 V or 1 V supply, your tolerances can drop to the neighborhood of 2%, requiring sub-milliOhm PDN impedance within the relevant bandwidth. This also requires significant decoupling in the PDN. This is why power and ground planes should be adjacent in your stackup, as this will provide sufficient decoupling when used alongside large decoupling capacitors.
Make sure to place power and ground planes on adjacent layers to provide sufficient decoupling.
What About Your Regulator?
One important aspect of system-level signal and power integrity in your PCB layout lies in your choice of regulator, particularly switching regulators. When a switching regulator switches and sources a large current, the EMI it produces can cause unintended switching in downstream digital components and can produce undesired frequencies in the output from the analog component. This requires sufficient isolation between the switching regulator and the components in your board. Additional filtration may be necessary as well in order to prevent strong switching noise from interfering with your components.
Low noise, low dropout regulators are ideal in systems where you are running at low levels, although you should measure the output from these regulators. You should ensure that they do not produce excessive conducted/radiated EMI as switching noise, and that they do not create an excessively large ripple on the PDN. This can be done with a test coupon or an evaluation board, and your measurements can be gathered with an oscilloscope and a near-field probe.
The link between system-level signal and power integrity in your PCB may not be obvious, but you can analyze your systems and design for signal/power integrity when you use the right PCB design and analysis software. Allegro PCB Designer and Cadence’s full suite of analysis tools can help you build stable boards for your new products and examine signal and power integrity throughout your next digital system.
If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.
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