SPICE Tools for Yield Optimization Simulation and Analysis

Key Takeaways

• Manufacturing processes cannot be simulated directly, but past data on yield from a manufacturing process can be used to estimate yield for a new product.

• Accurate yield estimation with SPICE requires simulating variations in component values or output electrical values.

• Advanced SPICE simulations can use Monte Carlo techniques to estimate manufacturing yield and determine whether your system will sit within your desired yield.

Yield optimization simulations require statistical analysis of the manufacturing process and tolerances in your electrical system.

Yield optimization is all about ensuring your product will meet the required specifications given the variance in a manufacturing process. Manufacturers implement statistical process control to try to locate and eliminate product defects caused by the manufacturing process. For circuit design, you need to consider component tolerances and layout tolerances to determine whether your new product will meet the required specifications.

How can you estimate yield without perfect knowledge of the manufacturing process or direct statistical data? You can use component tolerances and statistical process values to determine yield and identify areas of your design that need to change to reduce or accommodate tolerances. This is all based on Monte Carlo simulations for component and process tolerances. Here’s how you can create and run these simulations for your new products to estimate manufacturing yield.

Yield Optimization Simulation Requires Tolerance Values

Yield optimization requires estimating the manufacturing yield for your new product, which requires tolerance values on components and the manufacturing process. When we say “process tolerance,” we mean variations in the geometry of a trace, via, pad, or another element in a fabricated PCB. Determining these tolerances is your first task in yield optimization simulation.

Component Tolerances

Your component tolerances can be included in a Monte Carlo simulation by looking at nominal ratings and their stated tolerances. The nominal value can be taken as the mean in the probability distribution for a component value, and the rated tolerance value can be used to determine the variance for the components probability distribution. 

Be careful here, as the rated tolerance is normally stated as a 95% confidence level for a normal distribution. Unless you know otherwise, you should assume this confidence level is used for listing component tolerance values. You can convert back to the standard deviation in your component values by using the following formula:

Conversion between rated component tolerance and standard deviation for yield process optimization.

Process Tolerances

Some PCB manufacturers will provide process tolerances for layout features, such as drill hit location, trace width, pad size, and other features. However, it’s impossible to account for all of these variations in a SPICE yield optimization simulation. 

Here, trace width is important for transmission lines as this will create variations in the characteristic and differential impedance values. These points are also very important for passive RF components (e.g., filters, couplers, dividers, etc.) as these process variations will create variations in the transfer function and resonance frequencies for these components.

Variations in impedance and resonance spectra then affect things like impedance matching, antenna efficiency, insertion and return losses, and any other specification that depends directly on trace or via geometry. Rather than incorporate process tolerances directly into a circuit schematic, you need to calculate how the tolerance value creates a variation in the relevant performance metric. 

You can do this simply by taking your desired performance metric value as the statistical mean and then manually calculate the maximum and minimum performance metric values using the trace/via geometry tolerances provided by the manufacturer. This can be done using the formula listed above.

Using Tolerances in a Monte Carlo Simulation

A Monte Carlo simulation will randomly generate normally distributed component ratings using the distribution parameters you determine in the previous section. As these random values are generated, the circuit you’re designing is simulated and your output value or performance specification is measured. Yield optimization is also simplified by the fact that component tolerances and process tolerances are independent random variables—there is no conditional distribution relating component and process values.

The results you measure in your circuit simulation can be displayed in a scatter plot or a histogram. From here, you can determine a yield curve for your system. This curve tells you the probability that a manufactured unit will have the specification shown on the x-axis of your yield curve. An example histogram is shown below. Once you have this curve, you can determine a yield estimation using an integral.

Example histogram showing circuit measurements resulting from process and component variations.

Final Yield Estimation

Estimating the end manufacturing yield requires considering the effects of manufacturing and component tolerances on your important output specifications. Take a switching regulator module as an example. You might desire that your regulator have some maximum ripple value at the nominal voltage output, but component tolerances will cause this ripple value to vary. 

Take a transmission line in your layout as another example. Variations in the trace width will create variations in impedance, which will affect return loss and insertion loss due to impedance matching at the output.

Once you have your Monte Carlo results, you can use some basic statistical analysis to estimate manufacturing yield. If your yield is too low, you can opt for different components or make larger changes to your design. You can also judge whether your manufacturer’s tolerances are acceptable for your desired yield. This is especially important for your board layout, as the best manufacturers will publish layout tolerances for their clients.

Estimating yield in the face of multiple tolerances relies on taking an integral of your estimated yield curve. The yield curve for the specification of interest will typically be a normal distribution, as long as the system of interest is linear time-invariant. Otherwise, the distribution may not be normal and you’ll need to calculate the integral of the distribution curve numerically. However, the interpretation of the result is always the same; this integral is equal to the percentage of units that will meet your performance specification.

Normal Yield Curve Example

For a normally distributed yield curve, the integral of a normal distribution is just the error function or complementary error function. For the example of a voltage regulator with maximum allowed ripple, the yield would just be the area under the probability distribution for the ripple value up to the maximum allowed ripple. An example is shown below.

Example yield curve for the ripple from a power regulator. All ripple values below the desired VR(max) value are acceptable, so the yield integral includes all ripple values up to VR(max).

In the example above for output ripple from a power regulator, the yellow area under the curve is equal to the fraction of manufactured regulators that will have output ripple within the desired maximum ripple specification. The mean and variance can be easily calculated using regression or with elementary statistics formulas using your numerical simulation data.

When maximum and minimum values are specified, or if only a minimum value is specified, the yield will involve the complementary error function. The error function and complementary error function can be calculated in Excel or a more advanced statistics program. If your yield does not meet or exceed your desired yield, you need to go back and redesign the circuit with different components and/or tighter layout specifications.

When you need to design and run a yield optimization simulation, or other circuit simulations, you’ll need to use the best PCB design and analysis software to create your circuits and evaluate their functionality. The front-end design features from Cadence integrate with the powerful PSpice Simulator to create the ideal system for circuit design and evaluation. Once you’ve created a layout, Cadence has a suite of SI/PI Analysis Point Tools for post-layout verification and simulation. You’ll have all the features you need for design and optimization.

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.