Best Practices: Working with IDF

Today's printed circuit boards require tighter integration between electrical engineering and
mechanical engineering. This is a result of increasing component density and mechanical
complexity, as well as an increasing number of mechanical constraints such as PCB outline,
holes, slots, cutouts, keepouts, interconnects, heatsinks, and so on.

In the past, most ECAD engineers created board outlines from paper drawings that were
created by MCAD engineers. Now, this error-prone and time-consuming task can be
simplified and automated using the Cadence IDF 3.0 translator.

For additional information, see Intermediate Data Format in the Allegro PCB and Package
User Guide: Transferring Logic.

This paper describes the process of transferring data between Allegro PCB Editor and PTC
Pro/ENGINEER™ using the Cadence IDF 3.0 translator. It also:

• Describes the basic flow of importing and exporting data, including using front-end tools such as Allegro Design Entry HDL.
• Explains how information is interpreted by Allegro PCB Editor.
• Shows how Allegro PCB Editor and Pro/ENGINEER detects changes.