Issue link: https://resources.pcb.cadence.com/i/1532920
Note: The behavior of the trace will be such that when you're routing it, the trace thickness will change to maintain the impedance, or at least a DRC error will appear if your trace falls outside the target impedance range. Reason: Controlled impedance is crucial for maintaining signal integrity in high-speed circuits. It helps minimize signal reflec- tions, reduce crosstalk, and ensure proper signal transmission. Specify target impedance values (e.g., 50Ω for single-ended traces, 100Ω for differential pairs) to minimize reflections and ensure compatibility with specific communication protocols. This involves controlling trace width, spacing, and dielectric properties. Impact on the Board: f Improves signal quality and reduces distortion in high-speed signals (by reducing reflections) f Enhances overall system performance and reliability f It may require specific PCB materials and manufacturing processes to achieve the desired impedance values f Can influence trace routing and layer stack-up decisions By implementing proper impedance control constraints, designers can ensure that high-speed signals maintain their integrity throughout the PCB, leading to more reliable and higher-performing electronic products. Crosstalk Mitigation: Maximum parallel trace length Diagram illustrating crosstalk between two traces running parallel to each other. (source: Sierra Circuits) Purpose: Limit the length that signal traces run parallel to each other to reduce coupling and crosstalk. This is especially crucial for high-speed differential pairs. The acceptable length depends on factors like trace spacing, layer stack-up, and signal frequency. In this example, you will learn how the Constraint Manager prevents excessive coupling among traces. Steps to Execute Constraints: 1. Open the Constraint Manager. 2. Navigate to the Electrical > Electrical Constraint Set > Routing > Wiring worksheet. 3. Scroll horizontally to the Max Parallel column, then in that same column, select the cell for any of the Electrical Constraint sets shown below. Then a Parallel Segments window will appear. 6 www.cadence.com OrCAD X Constraint Management Guide