Issue link: https://resources.pcb.cadence.com/i/1532920
5. In our case, the DP_DATA1 has the ECS1 Constraint set and the via limits applied. Notice how the actual number of vias on the DP_DATA1 differential pair are within the acceptable limit of vias established in the Electrical Constraint Set (ECS1). Impact: It is easy to forget so many important factors in PCB design that are all crucial for high-speed designs. For instance, for USB 3.2, it's strongly recommended to use no vias or layer transitions. However, if transitions (vias) are needed, to use no more than two. Constraining the number of vias ensures that we do not inadvertently introduce errors into our board because of forgetting the via limits. Let the constraint manager do the remembering for you as a designer. Example Constraints for Common Applications USB (Universal Serial Bus) Constraints 1. Define differential pair routing rules: a. Set your constraint set and rules in the Electrical > Electrical Constraint Set > Routing > Differential Pair worksheet. b. Then apply that constraint set to the relevant differential pair in the Electrical > Net Routing > Differential Pair worksheet (e.g. ECS1). 2. Next, set impedance control for high-speed signals so they automatically adjust their widths during layer transitions (sometimes our calculations for physical constraints on the differential pair don't always hold when stackup changes are made, but the field solver in the OrCAD X PCB software calculates the widths for us in real-time to fix this). a. Set the constraint and values for impedance in the Electrical Constraint Set > Routing > Impedance worksheet. b. For USB 2.0 and 3.2 you can set them at 50 Ohms with 2-10% tolerance (to be in the 100 Ohm differential impedance range) for single ended impedance (check with your manufacturer for tolerances they can provide for impedance). c. Follow the instructions on impedance constraints and application. 3. Establish length matching for data lines: 22 www.cadence.com OrCAD X Constraint Management Guide