Issue link: https://resources.pcb.cadence.com/i/1532920
a. For USB Data+ and Data- signal traces, follow the Differential Pairs setup sections for Basic setup, Spacing setup and high-speed constraint setup. 4. Configure EMC rules: a. For EMC, the differential pairs on USB 3.0 and higher usually need to be restricted to specific layers on the PCB. b. Refer to the Layer restrictions section of this document for instructions on how to set up the right layers for your USB signals. Double Data Rate (DDR) Constraints f Differential pair skew control ɢ Set your differential pair rules according to the basic, spacing and high-speed instructions for differential pairs in this document guide f Differential pair common-mode voltage constraints ɢ Refer to the dynamic and Static Phase control parameters in the high-speed differential pair sections f Set up length matching for address and control signals ɢ Please refer to the Length matching section of this document (utilizing relative propagation delays and driver pin settings) f Define timing constraints for setup and hold times ɢ Outside the scope of this document. Please refer to Cadence signal integrity guides and courses f Establish impedance control for data lines ɢ Please see the Impedance Control section of this document f Configure termination requirements ɢ Outside the scope of this document f Routing topology depending on the DDR protocol (DDR2, 3, 4, etc. like minimum spanning tree, T-topology, fly-by topology, etc.) ɢ Instructions found in the Wiring Topology section of this document Rigid-Flex PCB Constraints f Define bend radius limitations for flex areas ɢ Not applicable to the Constraint Manager guide f Set up layer stack rules for transition areas ɢ Found in the Layer restrictions section of this document f Establish component placement restrictions on flex sections (keep out) ɢ Found in the Component Spacing constraints section of this document f Establish routing areas (bend-only, non-bend, etc.) ɢ Not applicable to the constraint document - please see Rigid Flex guide f Configure VIA usage rules in flex regions ɢ Via Limits can be found in the Maximum via count section of this document ɢ Via rules for flex regions can be found in the Manufacturing Constraints section under DFF Constraint Set and Design sections. Please see the Manufacturing section for more step by step information on how to implement those constraints. 23 www.cadence.com OrCAD X Constraint Management Guide