Issue link: https://resources.pcb.cadence.com/i/1532920
6. Once done, that will create the pin pair underneath the signal in the worksheet (shown below). 7. Where it says All Driver/All Receivers, you can change the pin pair relationships to other options such as: a. Longest Pin Pair b. Longest Driver/Receiver c. All Drivers/All Receivers d. (Clear) 8. For this example, we selected All Drivers/All Receivers. After that, you repeat the previous steps to create more pin paired nets, then to put your nets into a matched group. 9. To put nets into a matched group, click hold and drag the mouse to highlight all the nets of interest (DDR_DQ0 through DDR_DQ31 in this case), then right click any of them, choose Create - Match Group. A new window would appear. 10. Give the match group a name, like DDR_DQ, then click OK (Ensure that the Preserve Existing Membership checkbox is enabled). 11. The group gets created and is shown in the worksheet. 12. To see the analysis of the routed traces with respect to their pin delays and Relative Delays, right click on the Match Group just created (DDR_DQ(32)), then choose Analyze. 13. There will be color codes (yellow if not in range, green if fully in range, red if problematic) to show you which traces are within tolerance of the longest Driver Receiver pair. Impact: Prevents timing issues and ensures reliable data transmission for parallel signal communication (e.g. DDR3). 13 www.cadence.com OrCAD X Constraint Management Guide