Issue link: https://resources.pcb.cadence.com/i/1532920
Length Matching Purpose: Ensuring that traces carrying related signals are of equal length. Matching the lengths of data lines in a memory interface to ensure synchronized data transfer. Diagram showing matched-length traces on a PCB. Steps/Example: 1. Open the Constraint Manager. 2. First, ensure that the constraint manager is analyzing all the electrical constraints, pin delays, etc. in the Analysis Mode (from the menu select Analyze - Analysis Mode, choose all options in Electrical then click Apply then Okay). 3. Then navigate to this worksheet: Electrical > Net > Relative Propagation Delay. 4. In your design you will need to create a matched group for nets that are carrying parallel signals, like in the image below where we have DDR_DQ(32) having 32 nets. 5. But first, make a pin pair for all the nets you want to put into a matched group. For example, let's say you didn't have the DDR_DQ# signals in a match group yet. You would select something like the DDR_DQ0, right click it - Create - Pin Pair…, click OK when presented with the pin options. 12 www.cadence.com OrCAD X Constraint Management Guide