Issue link: https://resources.pcb.cadence.com/i/1436010
The Customer Faraday Technology Corporation (Faraday) is a leading fabless application-specific integrated circuit (ASIC) and silicon intellectual property (SIP) provider. It is one of the few leading ASIC / system- on-chip (SoC) vendors with a comprehensive, self-developed IP portfolio. These IP blocks help lower customers' integration risk and IP licensing costs, while shortening time to market. Furthermore, with its many years of experience in IP development, Faraday is equipped with robust IP customization flexibility and capabilities to meet customers' specific requirements, in terms of power, size, and performance. Established in 1993, Faraday has been acknowledged and applauded for its expertise and capabilities, with thousands of successful designs in a wide range of applications, covering consumer electronics, video (security surveillance), multimedia, flat-panel displays, communication, networking, and PC peripheral/storage, along with hundreds of millions of ASIC chips shipped annually worldwide. SoCs are undoubtedly becoming more complex and more integrated. To help customers tackle their SoC design challenges, Faraday provides expertise in the areas of IP, IP integration, IP verification, and hardware/software co-design at the system level, rather than at the chip level only. Faraday also takes the system level into consideration at the initial design stage, and provides Faraday-developed SoC platforms. The objective is to deliver high- quality and reliable solutions within the most competitive schedule. Until now, these platforms have facilitated many projects, including a highly complex, 300-million-gate SoC at the 40nm process node. Faraday Technology and Cadence "Using the hierarchical approach and partitioning guidelines reduced the number of days needed to run the 300-million-gate design prototyping process from two weeks to only three to five days." Kun-Cheng Wu, Associate Vice President, SoC Development and Service, Faraday Technology Business Challenge • Produce prototype of highly complex, 300-million-gate SoC—the 1st such effort in Taiwan—in 7 months • Grow business through ability to develop large-scale chip designs Design Challenges • Shorten verification and analyses processes • Process large database for huge SoC design • Manage and integrate different technologies across industries Cadence Solution • First Encounter ® Design Exploration and Prototyping • Encounter ® Digital Implementation System • Encounter Conformal ® Equivalence Checker • Incisive ® verification platform • Sigrity ™ packaging and PCB signal and power analysis solutions • Verification IP Catalog Results • Completed complex design from data-in to tapeout within 7 months • Reduced one iteration for timing optimization, extraction, analysis and verification of physical design down to 4 days • Expanded design capacity by 10X