Cadence PCB success stories

www.cadence.com 2 We leveraged UVM technology for both IP-level and system-level verification. Together with Cadence's VIP solution for interface, peripheral, and memory models, we achieved our goal of verification closure with good confidence on various SoC/IP products." Ken Liao, Associate Vice President, Digital System and Platform, Faraday Technology Corporation " The Challenge With the rise of cloud computing and the Internet of Things, there is more interlinking of people, devices, and data. Thus, the future is likely to see continued strong demand of network processors by professional industries. In 2011, Faraday undertook a 4G base station processor design project for a tier-one company. This is a large-size chip of more than 300 million logic gates. In terms of chip size, it is the first such effort for a Taiwanese company. This project encompassed front-end chip design to back-end implementation and manufacturing. This project truly tested Faraday's design and management capabilities for large-scale projects. Compared to the typical 12-million-gate USB3.0 chips, or the 25-million-gate projector chips on the consumer market, in this big-scale effort, the challenges were significant. This chip utilizes more than 100 internally designed and third-party IP, 5 6G SERDES IP, over 1,000 FCBGA package pins, and more than 20 process corners. At the same time, to be able to achieve a successful tapeout within seven months, every step had to be executed with the highest efficiency. For example, to run timing closure, the process from timing optimization to RC extraction, signal integrity (SI) analysis, and static timing analysis (STA) check had to be shortened to complete within four days. As another example of the challenges faced, in back-end verification, physical verification of the GDS files, as large as 70GB, had to be completed within two days. Kun-Cheng Wu, associate vice president of SoC Development and Service at Faraday, explained, "We have encountered three major design challenges, including managing a large database for a huge SoC design, striving for the highest efficiency to complete implementation and verification, and performing heterogeneous integration in different fields." Due to these design requirements, Wu said, "Faraday first implemented a hierarchical design system. This system allowed Faraday to integrate more efficient design procedures and the largest integrated design methods during the development stage. These efforts enabled us to overcome our challenges. And above all, using EDA tools effectively definitely played a very important role." The Solution Throughout this entire process, which included front-end SoC design to back-end chip development, Faraday utilized many solutions from Cadence, including: the Verification IP (VIP) Catalog, First Encounter Design Exploration and Prototyping, Encounter Digital Implementation System, Encounter Conformal Equivalence Checker, Incisive verification platform and Sigrity packaging and PCB signal and power analysis solutions. Ken Liao, associate vice president of Digital System and Platform at Faraday, was responsible for the front-end chip design, and said, "We worked closely with our customers during the front-end SoC design work. We repeatedly discussed specifications such as SoC infrastructure, chip memory, and performance. With such a large-scale and complex project, we needed to ensure that our customers could trust us to develop the best SoC, which plays a very critical role in silicon-embedded devices." He added, "We leveraged UVM technology for both IP-level and system-level verification. Together with Cadence's VIP solution for interface, peripheral, and memory models, we achieved our goal of verification closure with good confidence on various SoC/IP products." When embarking on the back-end design part, the first problem Faraday resolved was prototyping and feasibility analysis. As Wu pointed out, "Using the hierarchical approach and partitioning guidelines reduced the number of days needed to run the 300-million-gate design prototyping process from two weeks to only three to five days." Faraday used Encounter Digital Implementation for its floorplan analysis process. Wu commented, "As for the back-end design process, we were running against time. Every run needed to be completed in the shortest time possible and we had to be able to correct mistakes. During the entire design process, the Cadence team gave us plenty of support and recommendations. Their immediate support was extremely important to Faraday." He also pointed out, "For example, the top instance count of this design is 8 million. If we used optDesign to execute it, we would need 160 hours. But using optVirtual, we reduced the time to only 16 hours. And, after further reducing the instance count to 3.5 million with enhanced partitioning, we cut the time to only four hours. It was a 40X improvement in speed increment." "It was the same for the pre-CTS-opt stage. In 2011, Cadence's latest GigaOpt technology was not yet available. But Cadence provided us with its beta version of AAE (Advanced Analysis Engine), which eventually became GigaOpt, for a test run. For the 3.5 million top instance count design, the execution time was shortened from 72 hours by using optDesign to 24 hours. This is also an amazing improvement." "At that time, we frequently held meetings with Cadence's R&D team to discuss design, implementation, results, and functionalities. We hoped to be able to resolve our problems quickly. Cadence was always very supportive, and we consider it a perfect example of high-level R&D alignment for both companies."

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