Issue link: https://resources.pcb.cadence.com/i/1180268
Working with IDF Pro/Engineer Configuration Settings October 2019 35 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. 1 7200.00 -4400.00 0.00 1 7200.00 -2400.00 0.00 1 12000.00 -2400.00 0.00 1 12000.00 -4400.00 0.00 1 7200.00 -4400.00 0.00 .END_VIA_KEEPOUT .PLACE_KEEPOUTUNOWNED BOTH 1 8700.00 700.00 0.00 1 8700.00 3700.00 0.00 1 12000.00 3700.00 0.00 1 12000.00 700.00 0.00 1 8700.00 700.00 0.00 .END_PLACE_KEEPOUT .PLACE_REGIONUNOWNED TOP CPU 1 6700.00 4100.00 0.00 1 6700.00 8000.00 0.00 1 12000.00 8000.00 0.00 1 12000.00 4100.00 0.00 1 6700.00 4100.00 0.00 .END_PLACE_REGION .DRILLED_HOLES 36.00 -1700.00 2200.00PTHU1 PINUNOWNED 36.00 -1400.00 1800.00PTHU1 PINUNOWNED 36.00 -1400.00 1700.00PTHBOARD PINUNOWNED 36.00 -1400.00 1600.00PTHBOARD VIAUNOWNED 125.00 0.00 6000.00 PTH BOARD MTGUNOWNED 125.00 0.00 5000.00 NPTH BOARD TOOL UNOWNED 125.00 -1000.00 5000.00 PTH BOARD user UNOWNED .END_DRILLED_HOLES .NOTES 200.0011700.00 200.00 5500.00 "Demonstrating the translation to" 200.0011500.00 200.00 2000.00 "and from the IDF format." 200.0011300.00 200.00 2400.00 "These notes should appear on" 200.0011100.00 200.00 2000.00 "Board Geometry/IDF_Notes" .END_NOTES .PLACEMENT SOIC20WDEVICE?U1 -2500.00 2000.00 0.00 0.00TOPPLACED DIP14_3DEVICE?U2