OrCAD datasheets

OrCAD ® Sigrity ™ ERC (Electrical Rules Check) provides electrical rules checking technology that enables the PCB layout designer to easily and quickly identify signal quality issues and causes without the need for simulation models or extensive signal integrity expertise. Built using industry- and market-leading Cadence Sigrity technology, OrCAD Sigrity ERC goes beyond simple geometry- based design-rule checking (DRC), identifying signal quality issues that have typically only been uncovered by advanced SI/ PI tools. OrCAD Sigrity ERC is fully integrated with the OrCAD PCB Editor, allowing PCB designers to see issues within the PCB canvas, make a change, and validate the ERC has been corrected. Overview OrCAD Sigrity ERC empowers PCB layout designers to check and address signal quality issues that in the past have required complex SI simulation tools and SI engineers. Using ERC and simulation-based rule checking (SRC) during PCB layout can reduce overall design time by enabling signal quality issues to be found and addressed during PCB layout design, reducing the burden for SI experts. ERC- and SRC-based solutions are superior to DRC-based solutions in ensuring signal quality validation, identifying issues geometry-based DRCs often miss. OrCAD Sigrity ERC is specifi- cally designed for PCB layout designers leveraging industry- leading Cadence Sigrity technology, providing an easy-to-use interface with minimal setup and cross-probes with the PCB layout design. OrCAD Sigrity ERC delivers actionable results that identify and quickly address signal quality issues. Why Is ERC Superior to DRC? DRC-based signal quality checks usually use the design's dimen- sional information, such as length, width, distance, spacing, etc. They cannot validate the interconnect's electrical characteristics such as signals crossing split or different reference planes causing impedance changes. In contrast, ERC-based signal quality checks analyze at the individual, segment-level view in the geometry domain for signal quality, including: • Trace reference • Trace reference-aware impedance • Trace reference-aware coupling • Differential pair routing phase • Number of vias and via locations All analysis is organized for easy signal performance interpre- tation by the PCB layout designer, NOT the signal integrity (SI) expert. Highlights • No models required—easy to run by PCB layout designers • Detects impedance discontinuities of routed PCB signals • Detects excessive coupling between routed PCB signals • Integrated with OrCAD PCB Designer for easy modifi- cation of problem signals OrCAD Sigrity ERC Electrically aware rule checking for signal quality challenges

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