Issue link: https://resources.pcb.cadence.com/i/1480190
APPLICATION NOTE 6 Figure 8: State transitions during frequency-comparator operation The initialization/reset logic (INIT block) performs two functions. One distributes the effects of the INIT and RUN inputs, as defined in the stimulus include file, Freq_comparator.stm. The other uses the DONE signal from the error-detector to generate a RESET pulse; this has the same effect as the external RUN pulse–to restore the state machine to its starting state (0) as well as reset the cycle-detectors, timeout generator, and flip-flops in the error-detector. Normal operation then resumes. JEDEC file containing the programming for the PAL20RP4B OrCAD PLD 386 Type: PAL20RP4B * QP24* QF2568* QV1024* F0* L0000 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 * L0040 11 11 11 11 11 11 11 01 11 11 11 01 11 11 11 11 11 11 11 11 * L0080 11 11 11 11 11 11 11 11 11 10 11 11 11 11 11 11 11 11 11 11 * L0120 11 11 11 11 11 11 11 11 11 11 11 11 11 10 11 11 11 11 11 11 * L0320 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 * L0360 10 11 10 11 11 11 01 01 11 01 11 01 11 01 11 11 11 11 11 11 * L0640 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 * L0960 11 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 * L1280 11 11 11 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 * L1600 11 11 11 11 11 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 * L1920 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 * L1960 10 11 01 11 10 11 01 01 11 01 11 01 11 01 11 11 11 11 11 11 * L2000 01 11 01 11 01 11 01 10 11 10 11 10 11 11 11 11 11 11 11 11 * L2240 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 * L2280 01 11 01 11 10 11 01 01 11 01 11 01 11 01 11 11 11 11 11 11 * L2320 01 11 11 10 01 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 * L2560 11 11 11 11 * C4B0E* CCF0 Stimuli for the INIT, RUN, MODE, REFL, REFH, FTEST, and SYSCLK inputs * "frqchk.stm" stimulus file * uh1 stim (4,1111) $g_dpwr $g_dgnd + INIT RUN MODE REFL + IO_STM IO_LEVEL=0 + 0s 1100 + 2055ns 0100 + 2135ns 1000 + 2175ns 1000 + 2215ns 1000 + 2255ns 1100