APPLICATION NOTE
8
PSpice Simulation—PAL View
The transient analysis is defined with: Print Step = 1us and Final Time = 1ms. All flip-flops must be initialized in
the 0 state (rather than the default X state). This allows the simulator to properly initialize the circuit by forcing the
reset logic to a deterministic state (non X; the hardware implementation would eventually syncronize itself to the
input stimuli and operate correctly). In the top-level schematic, the SDL block is the only block with more than one
view. Without further setup, OrCAD Capture will generate the PSpice netlist using the DEFAULT gate-level view
for SDL. After running the simulation by PSpice, the state-machine operation is viewed in Probe by placing
markers on the appropriate wires and buses, or by typing the signal names in the Probe dialog under the
Trace/Add command as follows:
SYSCLK, REFH, REFL, FTEST
FAST, SLOW, OK, ERROR
{N3, N2, N1, N0} ;NEXT
{C3, C2, C1, C0} ;CURRENT
Figure 9 demonstrates the correct response of the circuit to the digital stimulus at FTEST.
Figure 9: Frequency-comparator output as FTEST input is Varied
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