PSpice Application Notes

APPLICATION NOTE 5 Operation The three frequency inputs–REFL, REFH, FTEST–each drive a separate instance of a cycle-detector circuit (PICD blocks). Each cycle-detector is made up of two pairs of D-type flip-flops and a few basic gates. After having been reset and enabled, the cycle-detectors output a HI level as soon as two similar edges (e.g., falling) have been applied. This indicates that one complete period of the input signal has been observed. The circuit implements a simple finite-state machine (see Figure 7) that recognizes the order in which the individual frequency inputs make complete cycles. Figure 7: A Complete Cycle For example, suppose that the REFH signal period is observed first (generating N1), followed by the REFL signal period (generating N2), then the FTEST period (generating N0). This indicates that the FTEST frequency is too low and that the SLOW output should be pulsed. But if the FTEST period is observed before the REFL cycle, an OK pulse is produced. The state machine current state simply represents the order of activity that has been observed since the last initialization or reset, which occurs every time any kind of output pulse is generated. The cycle-detectors monitor the input activity and produce the next state value (N3, N2, N1, N0), which is fed to the state-decoder (SDL block). At a rate determined by the system clock, SYSCLK, this next state becomes the current state; the 74154 4/16 decoders in the gate-level view of the state-decoder, continually provide unary logic indications of the next/current transitions (since next state values are not synchronized to SYSCLK). The random combinational logic in this same view recognizes the specific transitions that comprise the conditions of interest, i.e., FAST, SLOW, and OK, as per the state-transition diagram. (In the PAL view, the PAL20RP4B device replaces all of the decoding logic as well as the 4-bit register representing the current state value. The alternative implementations are functionally identical.) Note that the output indicators are not static state assignments; they are derived from selected state transitions. Thus, S14 þ S15 recognizes a SLOW condition, while S10 þ S15 signifies an OK condition. The error-detector logic (EDL block) waits for the TIMEOUT signal output by the timeout generator. The timeout generator is simply a counter whose Q3 output indicates that the 8th rising edge of the low frequency reference, REFL, has occurred. If none of the normal output indicators (SLOW, FAST, or OK) have occurred before TIMEOUT, the ERROR output is asserted. The error-detector also asserts its DONE output whenever any of FAST, SLOW, OK, or ERROR have occurred.

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