OrCAD datasheets

Allegro FPGA

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www.cadence.com 3 Allegro FPGA System Planner this is a manual process, mistakes that are not detected can also cause expensive physical prototype iterations. While it may help to automate the synchronization of changes made to the pin assignment by the FPGA designer, hardware designer, or PCB layout designer, it doesn't reduce the root cause of these iterations. Pin assignment that is not guided by all three aspects—FPGA resource availability, FPGA vendor pin assignment rules, and routability of FPGA pins on a PCB—requires many iterations at the tail end of the design process, thereby extending the time it takes to integrate today's complex, large-pin- count FPGAs on a PCB. Specifying design intent The Allegro FPGA System Planner comes with an FPGA device library to help with selection of devices to be placed. It uses OrCAD PCB Designer or Allegro PCB Editor footprints for the floorplan view and allows users to quickly create relative placement of the FPGA system components. The Allegro FPGA System Planner allows users to specify connectivity between components within the FPGA sub-system at a higher level through interface defini- tions. Users can create interfaces such as DDR2, DDR3, and PCI Express, and use these to specify connectivity between a FPGA and a memory DIMM module or between two FPGAs. The Allegro FPGA System Planner understands differential signals, and power signals, as well as clock signals. FPGA device rules The Allegro FPGA System Planner comes with a library of device-accurate FPGA models that incorporate pin assignment rules and electrical rules specified by FPGA device vendors. These FPGA models are used by the synthesis engine to ensure that the vendor-defined electrical usage rules of the FPGAs are strictly adhered to. These rules dictate such things as clock and clock region selection, bank allocation, SSO budgeting, buffer driver utilization, I/O standard voltage reference levels, etc. During synthesis, the Allegro FPGA System Planner automatically checks hundreds of combinations of these rules to ensure that the FPGA pins are optimally and accurately utilized. Placement-aware PIN assignment synthesis The Allegro FPGA System Planner provides users a way to create an FPGA system placement view using Allegro PCB footprints. Users specify connectivity between components in the placement view and the FPGA at a high level using interfaces such as DDRx, PCI Express, SATA, Front Side Bus, etc. that connect FPGAs and other components in the design, shortening the time to specify design intent for the FPGA system. Once the connectivity of the FPGA to other components in the sub-system is defined, the Allegro FPGA System Planner then synthesizes the pin assignment based on the user's design intent, available FPGA resources, component placement around the FPGA, and the FPGA vendor's pin assignment rules. The Allegro FPGA System Planner has a built-in DRC engine that incorporates the rules provided by FPGA vendors for pin assignment, reference voltages, and termi- nations. This rules-based engine prevents PCB physical prototype iterations as the FPGAs are always correctly connected. Pin assignment algorithms are optimized to assign interface signals to a group of pins, thereby minimizing net crossovers and improving routability on the PCB. Allegro FPGA System Planner Allegro Design Entry Allegro Part Library Symbols, Footprints FPGA Vendor Tools Allegro PCB Design Figure 3: The Allegro FPGA System Planner uses symbols and footprints from existing libraries Figure 4: The Allegro FPGA System Planner optimizes multiple FPGAs concurrently

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