OrCAD datasheets

www.cadence.com 4 Allegro FPGA System Planner Architectural exploration enabled During the device selection process, FPGA designers need a way to evaluate if the FPGA(s) they choose can meet their application needs while keeping the cost of devices as low as possible. Estimating FPGA resource requirements can be tricky and requires designers to balance look-up tables (LUTs), high-speed I/O requirements, and memory with I/Os for low-speed signals. Sometimes choosing more than one FPGA may be cheaper than choosing one large FPGA. While at other times, choosing an FPGA with a larger pin count will suffice, thereby saving board space and routing channels. Manual pin assignment approaches make performing these cost and performance tradeoffs very time consuming and tedious. With its placement-aware FPGA I/O pin assignment synthesis, the Allegro FPGA System Planner helps designers do tradeoffs quickly, enabling architectural exploration that is not practical with manual approaches. ASIC prototyping using FPGAs Some companies choose to do ASIC prototyping using FPGAs on the PCB. In these cases, the number of FPGAs used grows rapidly. This sometimes requires using several PCBs to place all the FPGAs. With a large number of FPGAs, the time to do initial pin assignment can be very long using manual processes. Additionally, without taking placement of these FPGAs into account, the pin assignment can make routing of the PCB a very long process, extending the time it takes for designers to get to the ASIC prototype using FPGAs. The Allegro FPGA System Planner shortens the time required to create pin assignment for a large number of FPGAs through placement-aware pin assignment synthesis that is driven by a device-accurate FPGA models library. With the ability to export port information in Verilog and import Verilog-based connectivity, the Allegro FPGA System Planner allows users to iterate with RTL partitioning software, shortening the time to define the FPGA-based system and quickly creating DRC-accurate FPGA pin assignment. Tight integration with Cadence design creation The Allegro FPGA System Planner generates Allegro Design Entry CIS and Allegro Design Entry HDL schematics for the FPGA sub-system. It uses existing symbols for FPGA in Allegro Design Entry symbol libraries. If the user desires, the Allegro FPGA System Planner can create split symbols for FPGA based on the connectivity or one split symbol per bank. Integration with FPGA vendor tools In addition to integration with Cadence PCB design tools, the Allegro FPGA System Planner communicates seamlessly with FPGA design tools. It generates and reads supported FPGA vendors' pin-assignment constraint files. This capability enables the FPGA designer to evaluate pin assignments against the functional needs of the FPGA. Any changes made by the FPGA designer to account for these requirements can be imported into the Allegro FPGA System Planner so that the complete set of pin assignments remain in sync. Optimizing FPGA pin assignments through Route Planning Mode The initial pin assignment—that accounts for placement and routability of the FPGA on a PCB—goes a long way toward reducing costly design iterations between FPGA designer, PCB layout designer, and hardware designer. Once the PCB layout designer starts to plan the routing of inter- faces and signals on FPGA, it is possible to further refine the FPGA pin assignment based on route intent, layer constraints, and fanout chosen for the FPGA. The Allegro FPGA System Planner allows users to optimize FPGA pin assignment during routing of the interfaces and signals on a FPGA by optimizing a set of signals tied to an interface based on the route approach. This optimization is performed by Allegro FPGA System Planner running as an engine under Allegro PCB Editor. Users have a choice of optimizing to the pin, to the break-out or completely reassigning the signals to a different bank. All of the pin reassignments are done in accordance with pin assignment rules provided by FPGA vendors. (See Figure 5) Scalability The Allegro FPGA System Planner technology is available in the following product offerings: • Allegro ASIC Prototyping Option— For companies that use FPGAs to prototype ASICs for synthesizing and optimizing pin assignment of more than four FPGAs at a time • Allegro 4 FPGA System Planner Option — For concurrent pin assignment, synthesis, and post-placement optimi- zation of up to four FPGAs at a time, access to Route Planning Mode to allow PCB designers to propose pin reassignments based on route approach to FPGAs (see feature matrix for additional information) • Allegro 2 FPGA System Planner Option —For pin assignment synthesis and post-placement optimization of a single FPGA • OrCAD FPGA System Planner— For optimum initial pin assignment synthesis of a single FPGA Figure 5: Optimizing FPGA pin assignments through route planning mode – before and after

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