OrCAD datasheets

www.cadence.com 2 Allegro FPGA System Planner the Allegro FPGA System Planner enables designers to explore their FPGA-based architecture and to create an optimum correct-by-construction pin assignment for either production or prototype designs that use FPGAs. The Allegro FPGA System Planner is integrated with the Cadence design creation tools: Cadence OrCAD ® Capture and Cadence Allegro Design Entry (CIS and HDL). It reads and creates schematic symbols for both OrCAD Capture and Allegro Design Entry HDL. In addition, a floorplan view uses existing footprint libraries for OrCAD PCB Designer and Allegro PCB Editor. Should placement change during layout, pin optimization using the Allegro FPGA System Planner can be accessed directly from the Allegro PCB Editor. Benefits • Scalable, cost-effective FPGA-PCB co-design solution from OrCAD to Allegro tools • Accelerates integration of FPGAs with OrCAD Capture and Allegro Design Authoring solutions • Shortens time for optimum initial pin assignment, accelerating PCB design schedules • Eliminates unnecessary, frustrating design iterations during the PCB layout process • Eliminates unnecessary physical prototype iterations due to FPGA pin assignment errors • Reduces PCB layer count through placement-aware pin assignment and optimization • Planning mode allows PCB designers to propose FPGA pin (re)assignments based on route planning, reducing number of layers or time to route designs or both Features Allegro FPGA system planner technology An FPGA system is defined as a subset of the PCB design that includes one or more FPGA and non-FPGA components that are connected to FPGAs. Traditional approaches to pin assignment are typically manual and often based on a spreadsheet. Tools such as these require users to do pin assignment without taking into consideration the placement of other components and routability of the inter- faces and signals. Above all, there is no online rules-checking to ensure that the right pin types are being used for the signals that are assigned to the FPGA pins. As a result, users have to make several iterations between the spreadsheet-based tools and the tools from FPGA vendors. Often this adds an increased number of iterations between the PCB layout designer who cannot route the signals from FPGA pins on available layers and the FPGA designer who has to accept paper-based or verbal pin-assignment suggestions from the PCB layout designer. Once a change is made to the pin assignment by the FPGA designer, the pin assignment change has to be made in the schematic design by the hardware designer. Such itera- tions add several days if not weeks to the design cycle and possibly a great deal of frustration for the team members. Since Figure 1: Color-coded map of the I/Os of a multi-bank FPGA with different types of configurable pins I/O Configurable Clock Capable Differential Power Figure 2: Placement/floorplan view provides users relative placement of critical components for optimum pin assignment synthesis

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