Cadence PCB Best Practices

Working with Real-Time DFA Analysis

Issue link:

Contents of this Issue


Page 6 of 28

Working with Design Partitions Design Partitioning October 2019 7 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. Command Location The design partition application commands are located in the Allegro PCB Editor Place – Design Partition menu: ■ Create Partitions ■ Workflow Manager ■ Guideports ■ Soft Net Assignment Understanding Team-based Applications and Restrictions This section describes uses and restrictions for Allegro PCB Editor applications and settings that pertain to design partitioning. All members, including the master designer, must understand the capabilities of the commands to which they have become accustomed when designing in single environment mode. Failure to understand these usage models may result in a loss of productivity across the team. Logic – Only the master designer can import logic when all the partitions are checked in or retracted. The master designer cannot import logic while partition designs are active. Partition designers cannot edit logic at any time. Stackup – The partition designer has read access to the stackup editor, but cannot rename or re-order layers when partition files are active. Design Parameters – The partition designer inherits unit, size, and accuracy parameters but cannot edit them. Colors and Grid Settings – The partition designer inherits database settings but is free to customize them. Changes made by the partition designer are not imported back to the master designer. Constraints (Electrical and Physical) – Prior to release 16.6, the master designer was responsible for entering all constraints. The Partition Designer has read access to these constraints but cannot create or override existing ones. The partition designer can override line width values during the etch edit session. There are no restrictions on setting DRC modes. New in SPB 16.6, Partition Designers can edit Electrical, Physical and Spacing constraints as well as Net Class relationships.

Articles in this issue

view archives of Cadence PCB Best Practices - Working with Real-Time DFA Analysis