Cadence PCB Best Practices

Working with Real-Time DFA Analysis

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Working with Design Partitions Design Partitioning October 2019 18 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. in the x direction, use layer 3. If the set consists of more than two layers, or if more than one set is assigned to the net objects, periodic design refreshing becomes necessary. Refreshing is discussed in the The Team Design Process on page 20. Physical/Spacing Rules – The partition designer inherits rules that drive both physical and spacing attributes but is prevented from making changes to constraint sets unless the Edit_Cns option is enabled. The changing of cline width is permitted when using Route – Add Connect or Edit – Change commands. Electrical Rules – The partition designer inherits but cannot change electrical rules in the partition database unless the Edit_Cns option is enabled. Length/time budgeting is not controlled, so it could be possible for a designer to consume the entire constraint within a single partition. Cadence recommends frequent refreshing of partition databases to ensure the latest data is captured. Auto Routing – The Allegro PCB Router, previously known as SPECCTRA, can be used within a partition area. The partition boundary is seen as a wire keepin area by the router. Auto-routing to the boundary requires guideports be in place. Guideports have the FIXED T TOLERANCE property set to 0 to prevent them from moving. The Route – Fanout by Pick, Route – Nets by Pick, and Route – Elongation By Pick commands in the Allegro PCB Editor Route menu are available to the partition designer. Caution Routing electrically constrained signals to the boundary may consume the entire constraint budget. Best practices for auto routing success recommends routing the entire board as a whole, not in sections. Partition Strategy for Testability The master designer is responsible for setting up parameters and executing Testprep in automatic mode. Enhancements made to Testprep in previous releases can help reduce the number of incremental passes when in automatic mode and produce higher-quality, lower- cost fixtures. The partition designer can only use manual processes for adding testprobes. To prevent conflicts, a testprobe added in a partition area is prefixed with the partition name: partition_1_TP1, for example. Before exporting the design, the master designer should consider setting the following parameters, properties, and DRC settings to maximum the team's efficiency.

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