Using Design Entry HDL designs in Allegro System Capture
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Overview
In most new products being developed, there is a significant part of existing design
data that gets reused. A substantial part of existing design data would be in Allegro
Design Entry HDL (DE-HDL). As Allegro System Capture is a new entrant in the
design capture domain, this necessitates the requirement of easily and quickly
adding DE-HDL designs to System Capture projects.
System Capture designs are DML-independent, whereas DE-HDL designs can be
DML-dependent, or DML independent. Before importing a DE-HDL design in
System Capture, ensure that it's in the DML-independent state.
Device Modeling Language
DML is a Cadence proprietary Device Modeling Language that provides
information about:
• Electrical characteristic of interconnect with IC
• Behavior of all ICs (V-I, V-T curves) for which IBIS model are available
o IBIS models are converted to DML
• Behavior of discrete devices with Spice models
• Buffer models characteristics
• Extended nets (XNets) definition
• Differential pairs (diff pair) definition
In setups where the simulation flow is not used, the DML models are used only for
defining XNets and Differential Pairs. Operating in DML-independent mode
eliminates the need to define DML models for create XNets or Differential Pairs.
