Allegro PCB Designer RAKs

Enabling CM Existing Design with Constraints Added in PCB Layout

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Enabling CM on Existing Schematic Design with Constraint Added in PCB Layout: RAK Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 4 Purpose This RAK outlines the process and procedures required to work on the existing Capture schematic design after Constraint Manager (CM) has been introduced in Capture. It explains how you can migrate constraints from a physical layout to the Capture schematic and how you can define constraints on different logical connections like nets, net groups, and buses. Audience This Document is intended for the PCB designers or engineers who create the schematic and want to make it constraint-driven. It explains everything about migrating and defining constraints on the existing Capture schematic design. Introduction A constraint is a user-defined requirement applied to a net or pin-pair in a design. To capture constraints, Cadence provides a tool named Constraint Manager, which is now integrated into OrCAD Capture. You can use CM with Cadence logic design tools, System Connectivity Manager, and OrCAD Capture, to capture and manage constraints while implementing logic. This document illustrates an example to assist in understanding how to migrate the constraints from an existing physical layout to the schematic in Capture. This module covers the following: ◼ Migrating constraints from the physical layout to the schematic ◼ Defining constraint properties on nets ◼ Creating a matched group and assigning constraints ◼ Creating pin pairs ◼ Using the 'Find' utility to locate CM objects in the schematic ◼ Creating a netlist and migrating new constraints to the Allegro layout This workshop will work with SPB17.4 or a higher release.

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