Allegro PCB Designer RAKs

Enabling CM on Existing Schematic Design with Constraint Added in PCB Layout: RAK Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 3 Contents Purpose...................................................................................................................................... 4 Audience .................................................................................................................................... 4 Introduction................................................................................................................................ 4 Download ................................................................................................................................... 5 Lab Set Up................................................................................................................................. 5 Capture Set Up ......................................................................................................................... 5 Allegro Set Up ........................................................................................................................... 5 Module 1: Migrati ng Constrai nts from Physical Layout to Schematic .............................. 6 Module 2: Buses and Net Groups i n Capture CM ............................................................. 10 Module 3: Defini ng Constraint Properties on Nets............................................................ 12 Module 4: Creating a Matched Group and Assigning Constraints ................................. 13 Module 5: Creating Pin Pairs ................................................................................................ 15 Module 6: Viewing Topology usi ng SigXp Flow ................................................................ 17 Module 7: Usi ng Find Utility to Locate Constraints on Design ........................................ 23 Cross-Probe from the Fi nd Wi ndow ................................................................................ 25 Module 8: Updati ng Board File with Design Sync (ECO) ................................................ 27 Support..................................................................................................................................... 28 Feedback ................................................................................................................................. 28

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