System Capture RAKs

Reuse Flow in Allegro Design Entry (Capture CIS)

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Reuse Flow in Allegro Design Entry CIS (Capture CIS) – Allegro PCB Editor Learn more at Cadence Support Portal - https://support.cadence.com © 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Page 16 Placing Hierarchical part 1. Choose Place -- Part and browse to the library bot2.olb you created and place the part LPF from it. If implementation path is correct you should be able to descend to bot2.dsn. 2. Make the connections to H-block and H-part to complete the design Annotating the External/Main Design 1. Select top.dsn and chose Tools -- Annotate. 2. Select PCB Editor Reuse tab and check Renumber design for using reuse module. You will get the list of all referenced schematics at the bottom of the dialog box under Select modules to mark for reuse. Check these designs. Within top.dsn, you must get bot1.dsn and bot2.dsn. 3. Click OK to annotate this design to renumber this design for reusing the modules.

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