Reuse Flow in Allegro Design Entry CIS (Capture CIS) – Allegro PCB Editor
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Referencing the Reuse Schematics from the
External/Main Design
You will create a design, top.dsn, which will use both the designs, bot1.dsn and
bot2.dsn. These reusable designs will be externally referenced from within top.dsn.
Bot1.dsn will be referenced using an H-block. Bot2.dsn will be referenced using an H-
part.
1. Open top.dsn in Capture from lab\.
2. Make sure that design level (Only PCB Design) is checked if you want to use the
auto reference feature. This option is at Options -- Preferences -- Miscellaneous.
If the option is unchecked, check it and then restart Capture.
Design level Annotation
You should use Design Level annotation for the main design (top.dsn), which is
referencing the external schematics. This option makes the annotation process easier if
you want to use the auto reference feature. It ensures that top.dsn will not get duplicate
references, avoiding lot of manual work to change references. This checkbox is at
Options -- Preferences -- Miscellaneous. If the option is unchecked, check it and then
restart Capture.
