Creating an Electrical Constraint Set for DDR3 signals:
1. Right click on the Dsn element named HSD_FPGA.
2. Choose Create > Electrical CSet…
3. Name it DDR3_DATA.
4. Set the following columns in the worksheet to:
a. Schedule = blank
b. Stub Length = 0.127 mm (when really it should not have stubs ideally)
c. Max Exposed Length = 0.1 mm (for solder mask clearance purposes)
d. Layer Sets = LS2, where you would create a layer set and choose only the Top and Bottom layers (as shown)
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OrCAD X High-Speed Digital Design Guide
