Once finished, you get the LS1 added to the allowed layer sets for that Electrical Constraint Set (ECS). Clocks are sensitive
signals, so you can set the DDR3_CK1N constraint set to use that LS1 layer set as well (see below).
Notice in the image above that our ECS which is named DDR2_A0 already has a Schedule assigned to it. This is possible if you
import or manually define a Schedule, but that is outside the scope of this document. We will define a new ECS of our own for
the DDR3 signals.
15 www.cadence.com
OrCAD X High-Speed Digital Design Guide
